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参数资料
| 型号： | LTC3775IUD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-QFN |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3775
APPLICATIONS INFORMATION
the upper MOSFET ’s R DS(ON) is used to sense current,
connect the SENSE pin to the source of Q T (the SW node).
Alternatively, for accurate current sensing, connect this pin
to a sense resistor located at the drain of Q T . The reference
input of CTLIM is connected to the I LIMT pin. Connect an
external resistor, R ILIMT , from the I LIMT pin to V IN to set
the the current limit threshold. The voltage at the SENSE
pin drops as the inductor current increases. CTLIM trips
if the voltage at the SENSE pin goes below the voltage at
the I LIMT pin causing TG to pull low and turn off Q T .
The bottom current limit comparator, CBLIM, monitors
the current through the bottom MOSFET, Q B , when BG
is high. If the inductor current exceeds the current limit
threshold when Q B is on, Q B remains on until the current
drops below the threshold. The SW pin is the input for
CBLIM. The reference input to CBLIM is derived from
the voltage at the I LIMB pin. Connect an external resistor,
R ILIMB , from the I LIMB pin to SGND to set the current limit
threshold.
The inductor current ?ows from PGND to SW when Q B is
on (for a positive load current). The SW node is therefore
a negative voltage. The LTC3775 inverts the voltage at the
SW pin before comparing it with the attenuated voltage
(5 × ) at the I LIMB pin. BG stays high once CBLIM trips and
TG remains low until the inductor current drops below
the threshold. Figure 5 shows typical waveforms during
output overload.
I L
20A/DIV
0A LOAD
V SS
1V/DIV
Current Limit Blanking Time
The LTC3775 current limit circuit features a short blanking
time following low-to-high and high-to-low transitions at
the SW node. This prevents false tripping of the current
limit circuit if there is ringing on the SW node.
When the top gate, TG, goes high, the topside comparator,
CTLIM, waits for 200ns before turning on to monitor the
SENSE voltage. Likewise, when the bottom gate, BG, goes
high the bottom side comparator, CBLIM, waits for 200ns
before turning on to monitor the SW voltage. This means
that the minimum TG and BG pulse is slightly more than
200ns during current limit. These blanking times do not,
however, limit the duty cycle capability of the control loop.
The LTC3775 control loop is capable of operation with a
TG on-time as low as 30ns.
If a sense resistor is employed on the top side, the LTC3775
automatically lowers the CTLIM blanking time from 200ns
to 100ns. The CBLIM blanking time remains at 200ns. The
blanking time can be reduced when a sense resistor is used
because the SENSE pin connects to the drain of the top
MOSFET which rings less than the SW node. The LTC3775
detects that a sense resistor is employed by checking that
the SENSE pin stays high (equal to V IN ) when BG is high.
If the SENSE pin is connected to the SW node, SENSE will
be at 0V when BG is high.
The Current Sensing Input Pins
The SENSE and I LIMT pins are inputs to the top current
limit comparator, CTLIM. The top current limit threshold is
set by the resistor, R ILIMT , connected to the I LIMT pin and
the I LIMT pin 100μA pull-down current. R ILIMT should be
placed close to the LTC3775 and the other end of R ILIMT
should run parallel with the SENSE trace to the Kelvin
sense connection underneath the sense resistor, as shown
in Figure 6. The sense resistor should be connected to the
drain of the top power MOSFET and the V IN node using
short, wide PCB traces. Ideally, the top terminal of the
V IN = 12V
V OUT = 1.2V
C SS = 0.01μF
20μs/DIV
3775 F05
sense resistors will be immediately adjacent to the posi-
tive terminal of the input capacitor, as shown in Figure 7a.
FIRST PAGE CIRCUIT
Figure 5. Typical Waveforms During Output Overload
This path is a part of the high di/dt loop formed by the
sense resistor, top power MOSFET, inductor and output
capacitor.
3775fa
14
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