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参数资料
| 型号： | LTC3775IUD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-QFN |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3775
PIN FUNCTIONS
(QFN/MSOP)
I LIMT (Pin 1/Pin 3): Topside Current Limit Set Point. This
pin has an internal 100μA pull-down current, allowing
the topside current limit threshold to be programmed by
an external resistor connected to V IN . See Current Limit
Applications.
I LIMB (Pin 2/Pin 4): Bottom Side Current Limit Set Point.
This pin has an internal 10μA pull-up current, allowing
the bottom side current limit threshold to be programmed
by an external resistor connected to SGND. See Current
Limit Applications.
FB (Pin 3/Pin 5): Error Ampli?er Input. The FB pin is
connected to a resistive divider from V OUT to SGND. The
feedback loop compensation network is also connected
to this pin.
COMP (Pin 4/Pin 6): Error Ampli?er Output. Use an RC
network between the COMP pin and the FB pin to compen-
sate the feedback loop for optimum transient response.
SS (Pin 5/Pin 7): Soft-Start. Connect this pin to an external
capacitor, C SS , to implement a soft-start function. When
the voltage on the SS pin is less than the 0.6V internal
reference, the LTC3775 regulates the V FB voltage to the
SS pin voltage instead of the 0.6V reference.
FREQ (Pin 6/Pin 8): Frequency Set. A resistor connected
from this pin to SGND sets the free-running frequency of
the internal oscillator. See Applications Information section
for resistor value selection details.
SGND (Pin 7/Pin 9): Signal Ground. All the internal low
power circuitry returns to the SGND pin. All feedback and
soft-start connections should return to SGND. SGND should
be Kelvin connected to a single point near the negative
terminal of the V OUT bypass capacitor.
BG (Pin 8/Pin 10): Bottom Gate Drive. This pin drives the
gate of the bottom N-channel synchronous switch MOSFET.
This pin swings from PGND to INTV CC .
INTV CC (Pin 9/Pin 11): Internal 5.2V Regulator Output.
The gate driver and control circuits are powered from this
voltage. Bypass this pin to power ground with a low ESR ce-
ramic capacitor of value 4.7μF or greater (X5R or better).
SENSE (Pin 10/Pin 12): Topside Current Sensing Input.
Connect this pin to the switch node of the converter for
pin can be connected to a sense resistor at the drain of
the top MOSFET for more accurate current limit.
V IN (Pin 11/Pin 13): Main Input Supply. Bypass this pin
to PGND with a low ESR ceramic capacitor of value 1μF
or greater (X5R or better).
SW (Pin 12/Pin 14): Switch Node. Connect this pin to the
source of the upper power MOSFET. This pin is also used
as the input to the bottom side current limit comparator
and the zero-crossing reverse current comparator.
TG (Pin 13/Pin 15): Top Gate Drive. This pin drives the
gate of the top N-channel MOSFET. The TG driver draws
power from the BOOST pin and returns to the SW pin,
providing true ?oating drive to the top MOSFET.
BOOST (Pin 14/Pin 16): Top Gate Driver Supply. This pin
should be decoupled to SW with a 0.1μF low ESR ceramic
capacitor. An external Schottky diode from INTV CC to
BOOST creates a ?oating charge-pump supply at BOOST.
No other external supplies are required.
MODE/SYNC (Pin 15/Pin 1): Pulse-Skipping Mode Enable/
Sync Pin. This multifunction pin provides pulse-skipping
mode enable/disable control and an external clock input
for synchronization of the internal oscillator. Pulling this pin
below 1.2V (DC) or driving it with an external logic-level syn-
chronization signal disables pulse-skipping mode operation
and forces continuous operation. Pulling the pin above 1.2V
enables pulse-skipping mode operation. This pin has an
internal 50k pull-down resistor connected to SGND.
RUN/ SHDN (Pin 16/Pin 2): Enable/Shutdown Input. Pull-
ing this pin above 1.22V enables the controller. Forcing
this pin below 1.22V causes the driver outputs to pull
low. Pulling this pin below 0.74V forces the LTC3775 into
shutdown mode. While in shutdown, the INTV CC regulator
and most internal circuitry turns off and the supply current
drops below 14μA. This pin has an internal 1μA pull-up
current that allows the LTC3775 to power up if this pin is
left ?oating.
PGND (Exposed Pad Pin 17/Exposed Pad Pin 17): Power
Ground. The BG driver returns to this pin. Connect PGND
to the source of the bottom power MOSFET and the V IN
and INTV CC bypass capacitors. PGND is electrically iso-
lated from SGND. The exposed pad of the QFN and MSOP
top MOSFET R DS(ON) current sensing. Alternatively, this
8
packages is connected to PGND.
3775fa
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