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参数资料
| 型号： | LTC3775IUD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-QFN |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3775
APPLICATIONS INFORMATION
DECREASING
LOAD
CURRENT
0A
0A
0A
PULSE-SKIPPING MODE
0A
0A
0A
FORCED CONTINUOUS
3775 F09
Figure 9. Comparison of Inductor Current Waveforms for Pulse-Skipping Mode and Forced Continuous Mode
response at low load currents, constant frequency opera-
tion, and the ability to maintain regulation when sinking
current. See Figure 8 for a comparison of the ef?ciency
at light loads for each mode.
In pulse-skipping mode, the LTC3775 reverse-current
comparator, IREV , monitors the SW pin for zero crossing
when the bottom gate, BG, is high. It turns off BG if the
inductor current reverses and the SW voltage goes above
GND. To prevent false tripping due to ringing on the SW
node when BG is ?rst turned on, there is a blanking time
of 200ns similar to the bottom side current limit blanking.
Under certain light load conditions, if the TG on-time is
short, the inductor current may reverse during the IREV
blanking time but the LTC3775 will only turn off BG after
the blanking time.
In applications where a low value inductor is used, the
high di/dt of the inductor ripple current together with the
parasitic series inductance of the bottom MOSFET, Q B ,
and PCB trace inductance creates an opposing voltage to
the voltage drop across the R DS(ON) of QB. This can cause
IREV to trip early, before the inductor current reverses.
The parasitic series inductance of the PCB trace can be
minimized by connecting the SW pin closer to the drain
of Q B .
INTV CC Regulator
The LTC3775 features a P-channel low dropout linear
regulator (LDO) that supplies power to the INTV CC pin from
of the LTC3775’s internal circuitry. The LDO regulates the
voltage at the INTV CC pin to 5.2V when V IN is greater than
6.5V. The INTV CC pin must be bypassed to ground with a
low ESR (X5R or better) ceramic capacitor of at least 4.7μF.
Good bypassing is needed to supply the high transient
currents required by the MOSFET gate drivers.
An internal undervoltage lockout (UVLO) monitors the volt-
age on INTV CC to ensure that the LTC3775 has suf?cient gate
drive voltage. If the INTV CC voltage falls below the UVLO
threshold of 3.1V, the gate drive outputs remain low.
Thermal Considerations
The LTC3775 is offered in a 3mm × 3mm QFN package
(UD16) that has a thermal resistance R TH(JA) of 68°C/W
and the MSOP (MSE16) package has a thermal resistance
of 40°C/W. Both packages have a lead pitch of 0.5mm.
The regulator can supply up to 50mA of gate drive load cur-
rent. The expected LDO load current can be calculated from
the gate charge requirement of the external MOSFET:
I INTVCC = (f SW ) ? (Q G(QT) + Q G(QB) ) + 3.5mA
where:
3.5mA is the quiescent current of LTC3775
Q G(QT) is the total gate charge of the top MOSFET
Q G(QB) is the total gate charge of the bottom MOSFET
f SW is the switching frequency
the V IN supply. INTV CC powers the gate drivers and much
3775fa
16
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