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| 型号： | LTC3802EUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 20/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 73 |
| 系列： | PolyPhase® |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 850kHz |
| 占空比： | 92% |
| 电源电压： | 3 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3802
APPLICATIO S I FOR ATIO
and all resistors should have better than 1% tolerance. If
this is not possible and Burst Mode operation is required,
the potential at CMPIN can be set slightly higher than FB
by using a slightly bigger resistor from CMPIN to ground.
This removes the requirement of having expensive resis-
tors at the FB and CMPIN pins, at the expense of having a
higher Burst Mode ripple and slightly different overvolt-
age and power good thresholds. To ensure clean Burst
Mode operation, the CMPIN and FB resistive divider re-
quires good layout technique. Both resistive dividers must
be connected to the same nodes and away from high
current paths.
Low load current efficiency depends strongly on proper
Burst Mode operation. In an ideal system, the gate drive is
the dominant loss term at low load currents. Burst Mode
operation turns off all output switching for several clock
cycles in a row, significantly cutting gate drive losses. As
the load current in Burst Mode operation falls toward zero,
the current drawn by the LTC3802 falls to a quiescent
level—about 6.5mA. To maximize low load efficiency,
make sure the LTC3802 is allowed to enter Burst Mode
operation as cleanly as possible.
Operating Frequency/Frequency Synchronization
The LTC3802 controller uses a constant frequency, phase-
lockable internal oscillator with its frequency determined
by an internal capacitor. This capacitor is charged by a
fixed current plus an additional current that is proportional
to the voltage applied to the PLLLPF pin. When the PLLIN
pin is not used, an internal pull-down current source
forces PLLIN to ground and the controller runs at a fixed
550kHz switching frequency.
The phase detector used is an edge sensitive digital circuit
which provides zero degree phase shift between the exter-
nal and internal oscillators. This type of phase detector will
not lock up on an input frequency close to the harmonics
of the VCO center frequency. The output of the phase
detector is a complementary pair of current sources
charging or discharging the external filter network on the
PLLLPF pin. A simplified block diagram is shown in
Figure 6.
If the external frequency, f PLLIN , is greater than the oscil-
lator frequency, f OSC , current is sourced continuously,
pulling up the PLLLPF pin. When f PLLIN is less than f OSC ,
current is sunk continuously, pulling down the PLLLPF
pin. If f PLLIN and f OSC are the same but exhibit a phase
difference, the current sources turn on for a period corre-
sponding to the phase difference. Thus the voltage on the
PLLLPF pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor, C LP , holds the voltage. When
locked, the PLL aligns the turn off of the top MOSFET to the
falling edge of the synchronizing signal.
The loop filter components, C LP and R LP , smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components, C LP and R LP , determine how fast the loop
acquires lock. Typically R LP = 10k and C LP is between
0.01 μ F and 0.1 μ F.
The PHASMD pin determines the relative phases between
the TG1, TG2 and the PLLIN signals. When PHASEMD is
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
phase-locked loop consists of an internal voltage con-
trolled oscillator, a divide by 12 frequency divider and a
PHASEMD
LTC3802
V CC
phase detector. The voltage controlled oscillator monitors
the output of the phase detector at the PLLLPF pin. It
provides a linear relationship between the PLLLPF poten-
tial and the master oscillator frequency. A DC voltage input
from 0.5V to 1.9V corresponds to a 330kHz to 750kHz
master switching frequency.
PLLIN
PHASE DETECTOR
÷ 12
VCO
INTERNAL MASTER CLOCK
3806 F06
PLLLPF
R LP
C LP
Figure 6. Phase-Locked Loop Block Diagram
3802f
20
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