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| 型号： | LTC3802EUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 73 |
| 系列： | PolyPhase® |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 850kHz |
| 占空比： | 92% |
| 电源电压： | 3 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3802
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating
temperature range. (Note 3) V CC = PV CC = BOOST = 5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switcher Switching Characteristics
f OSC
Oscillator Frequency
PLLIN Open or V PLLIN = 0V
490
550
610
kHz
V PLLLPF = 1.2V
550
kHz
R PLLIN
PLLIN Pull-Down Current Source
V PLLLPF = 0V
V PLLLPF = 2.4V
250
650
330
750
5
400
850
kHz
kHz
μ A
I PLLLPF
Phase
Phase Detector Output Current
Sourcing Capability
Sinking Capability
TG1 ↓ vs PLLIN ↓
TG1 ↓ vs PLLIN ↓
TG2 ↓ vs PLLIN ↓
TG2 ↓ vs PLLIN ↓
f PLLIN > f OSC
f PLLIN < f OSC
PHASEMD Floats
V PHASEMD = 5V
PHASEMD Floats
V PHASEMD = 5V
–15
15
0
90
180
270
μ A
μ A
Deg
Deg
Deg
Deg
V PHASEMD
Shutdown Threshold
q
1.2
1.7
V
Floating
2.0
V
90 ° Phase Threshold
q
3.5
4.0
4.5
V
DC MIN
Minimum TG Duty Cycle
V PLLIN = 0V
q
0
%
DC MAX
Maximum TG Duty Cycle
V PLLIN = 0V, V CMPIN = 0.6V (Note 9)
q
86
89
92
%
t ON(MIN)
TG Minimum Pulse Width
BG Minimum Pulse Width
(Notes 7, 10)
V CMPIN = 0V (Note 9)
50
400
ns
ns
t NOV
R DS(ON)
Driver Nonoverlap
TG High R DS(ON)
TG Low R DS(ON)
BG High R DS(ON)
BG Low R DS(ON)
No Load
I OUT = 100mA (Note 7)
10
30
1.6
1.3
1.8
0.7
80
2.20
1.80
2.50
1.00
ns
?
?
?
?
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3802 is guaranteed to meet performance specifications
from 0 ° C to 70 ° C. Specifications over the –40 ° C to 85 ° C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: To ensure proper operation, PV CC and BV CC (V BOOST – V SW ) must
be greater than V GS(ON) of the external MOSFETs.
Note 6: Supply current in shutdown is dominated by external MOSFET
leakage and may be significantly higher than the quiescent current drawn
by the LTC3802, especially at elevated temperature.
Note 7: Guaranteed by design, not subject to test.
Note 8: Rise and fall times are measured using 10% and 90% levels. Delay
and nonoverlap times are measured using 50% levels.
Note 9: If V CMPIN is less than 90% of its nominal value, BG minimum
pulse width is limited to 400ns.
Note 10: The LTC3802 leading edge modulation architecture does not
have a minimum TG pulse width requirement. The TG minimum pulse
width is limited by the rise and fall times.
Note 5: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
3802f
4
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