参数资料
型号: LTC3802EUH#TR
厂商: Linear Technology
文件页数: 13/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电压模式
输出数: 2
频率 - 最大: 850kHz
占空比: 92%
电源电压: 3 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
LTC3802
APPLICATIO S I FOR ATIO
f C = Crossover frequency =
f Z 1 ( ERR ) = f LC =
f Z 2 ( RES ) = =
Theexternalinductor/outputcapacitorcombinationmakes
a more significant contribution to loop behavior. These
components cause a second order LC roll-off at the output
with 180 ° phase shift. This roll-off is what filters the PWM
waveform, resulting in the desired DC output voltage, but
this phase shift causes stability issues in the feedback loop
and must be frequency compensated. At higher frequen-
cies, the reactance of the output capacitor will approach its
choose:
f SW
10
1
2 π R 2 C 1
f C 1
5 2 π ( R 1 + R 3 ) C 3
ESR, and the roll-off due to the capacitor will stop, leaving
– 20dB/decade and 90 ° of phase shift.
Figure 1 shows a Type 3 amplifier. The transfer function of
this amplifier is given by the following equation:
f P 1 ( ERR ) = f ESR =
f P 2 ( RES ) = 5 f C =
1
2 π R 2 ( C 1 // C 2 )
1
2 π R 3 C 3
V COMP – ( 1 + sC 1 R 2 ) [ 1 + s ( R 1 + R 3 ) C 3 ]
sR 1 ( C 1 + C 2 ) [ 1 + s ( C 1 // C 2 ) R 2 ] ( 1 + sC 3 R 3 )
? f ?
? f ?
≈ 40 log 1 + ? C ? – 20 log 1 + ? C ? – 20 log ( A MOD )
? f LC ? ? f P 2 ( RES ) f P 2 ( RES ) – f Z 2 ( RES ) ?
? 1 + ? ? 1 + + ?
R 2 ? f C ? ? f C f Z 2 ( RES ) ?
? ?
f P 2 ( RES ) ?
? ? 1 +
? 1 + +
?
f ESR – f LC ? ?
?
?
=
V OUT
The RC network across the error amplifier and the
feedforward components R3 and C3 introduce two pole-
zero pairs to obtain a phase boost at the system unity gain
frequency, f C . In theory, the zeros and poles are placed
symmetrically around f C , and the spread between the
zeros and the poles is adjusted to give the desired phase
boost at f C . However, in practice, if the crossover fre-
quency is much higher than the LC double-pole frequency,
this method of frequency compensation normally gener-
ates a phase dip within the unity bandwidth and creates
Required error amplifier gain at frequency f C :
2 2
? f LC ? ? f ESR ?
≈ 20 log ?
R 1 ? f C f LC
f ESR f C
where A MOD is the modulator and line feedforward gain
and is equal to:
= ≈ 22 V / V
some concern regarding conditional stability.
If conditional stability is a concern, move the error
A MOD ≈
V IN ( MAX ) ? DC MAX
V SAW
30 ? 0 . 89
1 . 2
amplifier’s zero to a lower frequency to avoid excessive
phase dip. The following equations can be used to com-
pute the feedback compensation components value:
Once the value of resistor R1, poles and zeros location
have been decided, the value of R2, C1, C2, R3 and C3 can
be obtained from the above equations.
f SW = Switching frequency
V OUT
C2
f LC =
f ESR =
1
2 π LC OUT
1
2 π R ESR C OUT
R1
R B
C3
R3
FB
R2
C1
COMP
0
–1
GAIN
PHASE
+1
–1
FREQ
–90
–180
V REF
BOOST
–270
–380
3802 F01
Figure 1. Type 3 Amplifier Compensation
3802f
13
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