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参数资料
| 型号： | LTC3802EUH#TR |
| 厂商： | Linear Technology |
| 文件页数： | 22/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 850kHz |
| 占空比： | 92% |
| 电源电压： | 3 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3802
APPLICATIO S I FOR ATIO
on-resistance. MOSFET on-resistance is typically speci-
fied with a maximum value R DS(ON)(MAX) at 25 ° C. In this
case, additional margin is required to accommodate the
rise in MOSFET on-resistance due to self heating and
higher ambient temperature:
R DS(ON)(MAX) (T) = ρ T ? R DS(ON)(MAX) (25 ° C)
The ρ T term is a normalization factor (unity at 25 ° C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/ ° C as shown in
Figure 8a. For a maximum junction temperature of 100 ° C,
using a value ρ T = 1.3 is reasonable.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 8b).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V DS drain voltage, but can be
adjusted for different V DS voltages by multiplying by the
ratio of the application V DS to the curve specified V DS
values. A way to estimate the C MILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V DS voltage
specified. C MILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C RSS
and C OS are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
Top Gate Duty Cycle =
V OUT
V IN
Bottom Gate Duty Cycle = ? IN OUT ?
2.0
1.5
? V – V ?
? V IN ?
The power dissipation for the top and bottom MOSFETs at
maximum output current are given by:
1.0
0.5
P TOP =
V OUT
V IN
( I OUT ( MAX ) 2 ) ( ρ T ( TOP ) )( R DS ( ON )( MAX )
)
V GS
? ( R DR MILLER ) ?
)( C
+ V IN 2 ?
? PV
– V V TH ( IL ) ? ?
( ) ( )(
I OUT ( MAX ) 2 ρ T ( TOP ) R DS ( ON )( MAX )
0
–50 0 50 100 150
JUNCTION TEMPERATURE ( ° C)
3802 F08a
Figure 8a. Typical MOSFET R DS(ON) vs Temperature
V IN
MILLER EFFECT
V
P BOT =
? 1 1 ?
? CC TH ( IL )
? I OUT ( MAX ) ?
? 2 ?
+ ? f sw
V IN – V OUT
V IN
)
a b
Q IN
C MILLER = (Q B – Q A )/V DS
+
V GS
–
+ V DS
–
3802 F08b
where:
R DR = Effective top driver resistance
V TH(IL) = MOSFET data sheet specified typical gate
Figure 8b. Gate Charge Characteristics
threshold voltage at the specified drain current
3802f
22
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