参数资料
型号: LTC3826IUH#TRPBF
厂商: Linear Technology
文件页数: 8/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 585kHz
占空比: 99.4%
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
LTC3826
PIN FUNCTIONS
SENSE1 – , SENSE2 – (Pins 1, 9): The (–) Input to the
Differential Current Comparators.
PLLLPF (Pin 2): The phase-locked loop’s lowpass ?lter is
tied to this pin when synchronizing to an external clock.
Alternatively, tie this pin to GND, INTV CC or leave ?oating to
select 250kHz, 530kHz or 390kHz switching frequency.
PHASMD (Pin 3): Control Input to Phase Selector which
determines the phase relationships between controller 1,
controller 2 and the CLKOUT signal.
CLKOUT (Pin 4): Output Clock Signal available to daisy-
chain other controller ICs for additional MOSFET driver
stages/phases.
PLLIN/MODE (Pin 5): External Synchronization Input to
Phase Detector and Forced Continuous Control Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG1 signal to be synchronized
with the rising edge of the external clock. In this case, an
R-C ?lter must be connected to the PLLLPF pin. When
not synchronizing to an external clock, this input, which
acts on both controllers, determines how the LTC3826
operates at light loads. Pulling this pin below 0.7V selects
Burst Mode operation. Tying this pin to INTV CC forces
continuous inductor current operation. Tying this pin to
a voltage greater than 0.9V and less than INTV CC –1.2V
selects pulse skipping operation.
SGND (Pins 6, 33): Small Signal Ground common to both
controllers, must be routed separately from high current
grounds to the common (–) terminals of the C IN capaci-
tors. The Exposed Pad is SGND. It must be soldered to
PCB ground for rated thermal performance.
RUN1, RUN2 (Pins 7, 8): Digital Run Control Inputs for
Each Controller. Forcing either of these pins below 0.7V
shuts down that controller. Forcing both of these pins below
0.7V shuts down the entire LTC3826, reducing quiescent
current to approximately 4μA.
FOLDDIS (Pin 14): Foldback Current Disable Input Pin.
INTV CC (Pin 19): Output of the Internal Linear Low Dropout
Regulator. The driver and control circuits are powered
from this voltage source. Must be decoupled to power
ground with a minimum of 4.7μF tantalum or other low
ESR capacitor.
EXTV CC (Pin 20): External Power Input to an Internal LDO
Connected to INTV CC . This LDO supplies INTV CC power,
bypassing the internal LDO powered from V IN whenever
EXTV CC is higher than 4.7V. See EXTV CC Connection in
the Applications Information section. Do not exceed 10V
on this pin.
PGND (Pin 21): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky recti?ers and the (–) terminal(s)
of C IN .
V IN (Pin 22): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
BG1, BG2 (Pins 23, 18): High Current Gate Drives for Bot-
tom (Synchronous) N-Channel MOSFETs. Voltage swing
at these pins is from ground to INTV CC .
BOOST1, BOOST2 (Pins 24, 17): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the BOOST and SW pins and Schottky diodes are
tied between the BOOST and INTV CC pins. Voltage swing
at the BOOST pins is from INTV CC to (V IN + INTV CC ).
SW1, SW2 (Pins 25, 16): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V IN .
TG1, TG2 (Pins 26, 15): High Current Gate Drives for
Top N-Channel MOSFETs. These are the outputs of ?oat-
ing drivers with a voltage swing equal to INTV CC – 0.5V
superimposed on the switch node voltage SW.
PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is
pulled to ground when the voltage on the V FB1 pin is not
within ±10% of its set point.
Driving this pin high (to INTV CC ) disables foldback current
limiting during short-circuit or overcurrent conditions.
3826fc
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