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| 型号： | LTC3827IUH#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A DUAL SWITCHING CONTROLLER, 580 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封装： | 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-32 |
| 文件页数： | 16/36页 |
| 文件大小： | 451K |
| 代理商： | LTC3827IUH#TR |
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LTC3827
23
3827ff
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
PLLLPF PIN VOLTAGE (V)
0
FREQUENCY
(kHz)
0.5
1
1.5
2
3827 F09
2.5
0
100
300
400
500
900
800
700
200
600
APPLICATIONS INFORMATION
to PLLIN/MODE, is shown in Figure 9 and specied in the
Electrical Characteristics table. Note that the LTC3827 can
only be synchronized to an external clock whose frequency
is within range of the LTC3827’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplied block diagram
is shown in Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the lter capacitor, CLP, holds the voltage.
The loop lter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The lter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01μF.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
250kHz
Floating
DC Voltage
400kHz
INTVCC
DC Voltage
530kHz
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3827 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
tON(MIN) <
VOUT
VIN(f)
Figure 10. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
RLP
CLP
3827 F10
PLLLPF
EXTERNAL
OSCILLATOR
PLLIN/
MODE
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