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参数资料
| 型号： | LTC3833IUDC#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/36页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 20-QFN |
| 标准包装： | 91 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2.2MHz |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3833
OPERATION (Refer to Functional Diagram)
When the RUN pin is pulled low to disable the controller or
when INTV CC drops below its undervoltage lockout thresh-
old of 3.65V, the TRACK/SS pin is pulled low internally.
Light Load Current Operation
When the DC load current is less than 1/2 of the peak-
to-peak inductor current ripple, the inductor current can
drop to zero or become negative. If the MODE/PLLIN pin
is connected to SGND, the LTC3833 will transition into
discontinuous mode operation (also called pulse-skipping
mode), where a current reversal comparator, I REV , detects
and prevents negative inductor current by shutting off the
bottom MOSFET, MB. In this mode, both switches remain
off with the output capacitor supplying the load current.
As the output capacitor discharges and the output volt-
age droops lower, the EA will eventually move the ITH
voltage above the zero current level to initiate another
switching cycle.
If the MODE/PLLIN pin is tied to INTV CC or an external
clock is applied to MODE/PLLIN, the LTC3833 will be forced
to operate in continuous mode (called forced continuous
mode) and not transition into discontinuous mode. In this
case the current reversal comparator, I REV , is disabled, al-
lowing the inductor current to become negative and thus
maintain constant frequency operation.
Frequency Selection and External Clock
Synchronization
The steady-state switching frequency of the LTC3833 is
set by an internal oscillator. The frequency of this internal
oscillator can be programmed from 200kHz to 2MHz by
connecting a resistor from the RT pin to SGND. The RT
pin is forced to 1.2V internally. A phase-locked loop (PLL)
system synchronizes the TG turn-on to this internal oscil-
lator when no external clock is provided.
For applications with stringent frequency or interference
requirements, an external clock source connected to
the MODE/PLLIN pin can be used to synchronize the TG
turn-on to the rising edge of the clock. The LTC3833 oper-
ates in forced continuous mode when it is synchronized to
the external clock. The external clock frequency has to be
within ±30% of the internal oscillator frequency for suc-
cessful synchronization and the clock input levels should
be greater than 2V for HI and less than 0.5V for LO. The
MODE/PLLIN pin has an internal 600k pull-down resistor.
Power Good and Fault Protection
The power good pin, PGOOD, is connected internally to
an open-drain N-channel MOSFET. An external pull-up
resistor to a voltage supply of up to 6V (or INTV CC ) com-
pletes the power good detection scheme. Overvoltage
and undervoltage comparators OV and UV turn on the
MOSFET and pull the PGOOD pin low when the differen-
tial feedback voltage is outside a ±7.5% window of the
0.6V reference voltage. The PGOOD pin is also pulled low
when the LTC3833 is in the soft-start or tracking phase,
when in undervoltage lockout, or when the RUN pin is
low (shut down).
When the differential feedback voltage is within the ±7.5%
requirement, the open-drain NMOS is turned off and the
pin is pulled up by an external resistor. There is an internal
delay of 10μs before the PGOOD pin will indicate power
good once the differential feedback voltage is within the
±7.5% window. When the feedback voltage goes out of
the ±7.5% window, there is an internal 20μs delay before
PGOOD is pulled low. In an overvoltage condition, MT is
turned off and MB is turned on immediately without any
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is shorted
to ground. As the differential feedback voltage drops, the
current threshold voltage on the ITH pin is pulled down
and clamped to 1.2V. This reduces the inductor valley
current level to 1/4th of its maximum value as the differ-
ential feedback approaches 0V. Foldback current limiting
is disabled at start-up.
3833f
12
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