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参数资料
| 型号： | LTC3836EUFD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 28-QFN |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 825kHz |
| 占空比： | 97% |
| 电源电压： | 2.75 V ~ 4.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3836
APPLICATIONS INFORMATION
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the ?lter capacitor C LP holds the voltage.
5V supply is available. Note that in applications where the
supply voltage to C B exceeds V IN , the BOOST pin will draw
approximately 500μA in shutdown mode.
Table 2 summarizes the different states in which the
SYNC/FCB pin can be used
Table 2.
The loop ?lter components, C LP and R LP , smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The ?lter
components C LP and R LP determine how fast the loop
acquires lock. Typically R LP = 10k and C LP is 2200pF to
0.01μF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
SYNC/FCB PIN
0V to 0.5V
0.7V to V IN
External Clock Signal
CONDITION
Forced Continuous Mode
Current Reversal Allowed
Pulse-Skipping Operation Enabled
No Current Reversal Allowed
Enable Phase-Locked Loop
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
Fault Condition: Short-Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
Table 1.
PLLLPF PIN
0V
Floating
V IN
RC Loop Filter
SYNC/FCB PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked to External Clock
foldback current limiting can be added to reduce the cur-
rent in proportion to the severity of the fault.
Foldback current limiting is implemented by adding
diodes D FB1 and D FB2 between the output and the I TH
pin as shown in Figure 11. In a hard short (V OUT = 0V),
the current will be reduced to approximately 50% of the
maximum output current.
Topside MOSFET Drive Supply (C B , D B )
V OUT
In the Functional Diagram, external bootstrap capaci-
tor C B is charged from a boost power source (usually
V IN ) through diode D B when the SW node is low. When
1/2 LTC3836
I TH V FB
R2
R1
+
D FB1
D FB2
a MOSFET is to be turned on, the C B voltage is applied
across the gate-source of the desired device. When the
topside MOSFET is on, the BOOST pin voltage is above
3836 F11
Figure 11. Foldback Current Limiting
the input supply. V BOOST = 2V IN . C B must be 100 times the
total input capacitance of the topside MOSFET. The reverse
breakdown of D B must be greater than V IN(MAX) . Figure 6
shows how a 5V gate drive can be achieved if a secondary
3836fb
20
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| LTC3838EFE#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 38TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:2,000 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:50% 电源电压:9 V ~ 10 V 降压:无 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 包装:带卷 (TR) |
| LTC3838EFE#TRPBF | 功能描述:IC REG CTRLR BUCK PWM CM 38TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LTC3838EUHF#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 38-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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