参数资料
型号: LTC3836EUFD#TRPBF
厂商: Linear Technology
文件页数: 23/30页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 825kHz
占空比: 97%
电源电压: 2.75 V ~ 4.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-WFQFN 裸露焊盘
包装: 带卷 (TR)
LTC3836
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3836. These items are illustrated in the layout diagram of
Figure 13. Figure 14 depicts the current waveforms present
in the various branches of the 2-phase dual regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small
as possible and isolated as much as possible from the
power loop of the other channel. Ideally, the main and
synchronous FETs should be connected close to one
another with an input capacitor placed right at the FETs.
It is better to have two separate, smaller valued input
capacitors (e.g., two 10μF —one for each channel) than
it is to have a single larger valued capacitor (e.g., 22μF)
that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, I TH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the
synchronous N-channel MOSFET. Each channel should
have its own power ground for its power loop (as de-
scribed above in item 1). The power grounds for the
two channels should connect together at a common
point. It is most important to keep the ground paths
with high switching currents away from each other.
The PGND pins on the LTC3836 should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the V FB pins. The
trace connecting the top feedback resistor (R B ) to
the output capacitor should be a Kelvin trace. The I TH
compensation components should also be very close
to the LTC3836.
4) The current sense traces (SENSE + and SW) should be
Kelvin connections right at the main N-channel MOSFET
drains and sources.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-
signal components, especially the opposite channel’s
feedback resistors, I TH compensation components, and
the current sense pins (SENSE + and SW).
6) Connect the boost capacitors to the switch nodes, not to
the small signal nodes SWn. Connect the boost diodes
to the positive terminal of the input capacitor.
LTC3836EGN
C OUT1
L1
V OUT1
+ 28
1  SW1
2 N/C
SENSE1
BOOST1
27
C B1
3
4
5
6
7
IPRG1
V FB1
I TH1
IPRG2
PLLLPF
PGND
BG1
SYNC/FCB
TG1
PGND
26
25
24
23
22
D B1
M1
C VIN1
C VIN
M2
V IN
8
9
10
11
12
13
SGND
V IN
TRACK/SS2
V FB2
I TH2
PGOOD
TG2
RUN/SS
BG2
N/C
PGND
BOOST2
SENSE2 +
SW2
21
20
19
18
17
16
15
14
D B2
C B2
C VIN2
M3
L2
M4
C OUT2
3836 F13
V OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 13. LTC3836 Layout Diagram
3836fb
23
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