参数资料
型号: LTC3869EUFD#PBF
厂商: Linear Technology
文件页数: 18/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-QFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 850kHz
占空比: 95%
电源电压: 4 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-WFQFN 裸露焊盘
包装: 管件
LTC3869/LTC3869-2
APPLICATIONS INFORMATION
V OUT
f SW
? I LOAD(MAX)
V OUT
V IN – V OUT
( I MAX ) 2 ( ) R DS(ON) +
V OUT
V IN
( V IN ) 2 ? MAX ? ( R DR ) ( C MILLER ) ?
? ? 2
? ? f OSC
1 1
V TH(MIN) ? ?
? ? V INTVCC – V TH(MIN)
( I MAX ) 2 ( 1 + d ) R DS(ON)
P SYNC =
dutycyclesuptothemaximumof95%,usethefollowing
equation to find the minimum inductance.
L MIN > ? 1.4
where
L MIN is in units of μH
f SW is in units of MHz
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3869: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV CC
voltage. This voltage is typically 5V during start-up
(see EXTV CC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (V IN
< 5V); then, sub-logic level threshold MOSFETs (V GS(TH)
< 3V) should be used. Pay close attention to the BV DSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R DS(ON) , Miller capacitance C MILLER , input
voltage and maximum output current. Miller capacitance,
C MILLER , can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C MILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V DS . This result is
then multiplied by the ratio of the application applied V DS
to the gate charge curve specified V DS . When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V IN
Synchronous Switch Duty Cycle =
V IN
The MOSFET power dissipations at maximum output
current are given by:
P MAIN = 1 + d
? I ?
? 2 ?
? +
V IN – V OUT
V IN
where d is the temperature dependency of R DS(ON) and
R DR (approximately 2?) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V TH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V IN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for V IN > 20V the transition losses rapidly
increase to the point that the use of a higher R DS(ON) device
with lower C MILLER actually provides higher efficiency.
The synchronous MOSFET losses are greatest at high input
38692fa
18
For more information www.linear.com/LTC3869
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