参数资料
型号: LTC3869EUFD#PBF
厂商: Linear Technology
文件页数: 8/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-QFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 850kHz
占空比: 95%
电源电压: 4 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-WFQFN 裸露焊盘
包装: 管件
LTC3869/LTC3869-2
TYPICAL PERFORMANCE CHARACTERISTICS
T A = 25°C, unless otherwise noted.
60
Shutdown Current
vs Input Voltage
45
Shutdown Current
vs Temperature
3.8
Quiescent Current
vs Input Voltage without EXTV CC
50
40
30
20
10
40
35
30
25
20
15
10
5
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35 40
3869 G23
0
–50
–25
0 25 50 75
TEMPERATURE (°C)
100 125
3869 G24
1.8
5
10
15 20 25 30
INPUT VOLTAGE (V)
35 40
3869 G25
PIN FUNCTIONS
(UFD/GN)
RUN1, RUN2 (Pin 27, Pin 10/Pin 1, Pin 13): Run Control
Inputs. A voltage above 1.2V on either pin turns on the IC.
However, forcing either of these pins below 1.2V causes
the IC to shut down the circuitry required for that particular
channel. There are 1μA pull-up currents for these pins.
Once the RUN pin raises above 1.2V, an additional 4.5μA
pull-up current is added to the pin.
V FB1 , V FB2 (Pin 4, Pin 5/Pin 4, Pin 10): Error Amplifier
Feedback Inputs. These pins receive the remotely sensed
feedback voltages for each channel from external resistive
dividers across the outputs.
I TH1 , I TH2 (Pin 3, Pin 6/Pin 6, Pin 8): Current Control
Thresholds and Error Amplifier Compensation Points.
Each associated channels’ current comparator tripping
threshold increases with its I TH control voltage.
SGND (Pin 29/Pin 7): Signal Ground. All small-signal
components and compensation components should con-
nect to this ground, which in turn connects to PGND at
one point. Pin 29 is the exposed pad, only available for
the UFD package. The exposed pad must be soldered to
PCB ground for electrical connection and rated thermal
performance.
TK/SS1, TK/SS2 (Pin 2, Pin 7/Pin 5, Pin 9): Output Volt-
age Tracking and Soft-Start Inputs. When one particular
channel is configured to be the master of two channels,
a capacitor to ground at this pin sets the ramp rate for
the master channel’s output voltage. When the channel
is configured to be the slave of two channels, the V FB
voltage of the master channel is reproduced by a resistor
divider and applied to this pin. Internal soft-start currents
of 1.2μA are charging these pins.
MODE/PLLIN (Pin 25/Pin 27): Forced Continuous Mode,
Burst Mode Operation, or Pulse-Skipping Mode Selection
Pin and External Synchronization Input to Phase Detec-
tor Pin. Connect this pin to SGND to force both channels
in continuous mode of operation. Connect to INTV CC to
enable pulse-skipping mode of operation. Leave the pin
floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator with the
clock on this pin. The PLL compensation components are
integrated inside the IC.
38692fa
8
For more information www.linear.com/LTC3869
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