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参数资料
| 型号： | LTC3890EGN-1#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO28 |
| 封装： | LEAD FREE, PLASTIC, SSOP-28 |
| 文件页数： | 16/36页 |
| 文件大小： | 498K |
| 代理商： | LTC3890EGN-1#PBF |
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LTC3890-1
23
38901f
APPLICATIONS INFORMATION
Figure 10. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
Phase-Locked Loop and Frequency Synchronization
The LTC3890-1 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass lter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage at the VCO input is adjusted until
the phase and frequency of the internal and external oscil-
lators are identical. At the stable operating point, the phase
detector output is high impedance and the internal lter
capacitor, CLP, holds the voltage at the VCO input.
Note that the LTC3890-1 can only be synchronized to
an external clock whose frequency is within range of
the LTC3890-1’s internal VCO, which is nominally 55kHz
to 1MHz. This is guaranteed to be between 75kHz and
850kHz.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
350kHz
INTVCC
DC Voltage
535kHz
Resistor
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time dura-
tion that the LTC3890-1 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t
V
Vf
ON MIN
OUT
IN
() <
()
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY
(kHz) 600
800
1000
35 45 55
25
38901 F10
400
200
500
700
900
300
100
0
65 75 85 95 105 115 125
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