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参数资料
| 型号： | LTC4253AIGN#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封装： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16 |
| 文件页数： | 34/34页 |
| 文件大小： | 369K |
| 代理商： | LTC4253AIGN#PBF |
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LTC4253/LTC4253A
9
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the start-up cycle, the SS capacitor (CSS) is ramped by a
22A (28A for the LTC4253A) current source. The GATE
pin is held low until SS exceeds 20 VOS = 0.2V. SS is
internally shunted by a 100k RSS which limits the SS pin
voltage to 2.2V (50k resistor and 1.4V for the LTC4253A).
This corresponds to an analog current limit SENSE voltage
of 100mV (60mV for the LTC4253A). If the SS capacitor
is omitted, the SS pin ramps up in about 250s (140s
for the LTC4253A). The SS pin is pulled low under any of
the following conditions: UVLO at VIN, UV, OV, during the
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high.
SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin.
LoadcurrentismonitoredbyasenseresistorRSconnected
between SENSE and VEE, and controlled in three steps. If
SENSE exceeds VCB (50mV), the circuit breaker compara-
tor activates a (200A+8IDRN) TIMER pull-up current.
If SENSE exceeds VACL, the analog current-limit amplifier
pulls GATE down to regulate the MOSFET current at VACL/
RS.Intheeventofacatastrophicshort-circuit,SENSEmay
overshoot VACL. If SENSE reaches VFCL (200mV), the fast
current-limit comparator pulls GATE low with a strong
pull-down. To disable the circuit breaker and current limit
functions, connect SENSE to VEE.
VEE (Pin 8): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
GATE (Pin 9): N-channel MOSFET Gate Drive Output. This
pin is pulled high by a 50A current source. GATE is pulled
low by invalid conditions at VIN (UVLO), UV, OV, during the
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high. GATE is actively servoed to control
the fault current as measured at SENSE. Compensation
capacitor, CC, at GATE stabilizes this loop. A comparator
monitors GATE to ensure that it is low before allowing an
initial timing cycle, then the GATE ramps up after an over-
voltage event or restart after a current limit fault. During
GATE start-up, a second comparator detects GATE within
2.8V of VIN before PWRGD1 can be set and power good
sequencing starts.
DRAIN(Pin10):DrainSenseInput.Connectinganexternal
resistor,RDbetweenthispinandtheMOSFET’sdrain(VOUT)
allows voltage sensing below 6.15V (5V for LTC4253A)
and current feedback to TIMER. A comparator detects if
DRAIN is below 2.39V and together with the GATE high
comparator,setsthePWRGD1flag.IfVOUTisaboveVDRNCL,
the DRAIN pin is clamped at approximately VDRNCL. RD
current is internally multiplied by 8 and added to TIMER’s
200A during a circuit breaker fault cycle. This reduces
the fault time and MOSFET heating.
OV (Pin 11): Overvoltage Input. For the LTC4253, the
threshold at the OV pin is set at 6.15V with 0.3V hys-
teresis. If OV > 6.15V, GATE pulls low. When OV returns
below 5.85V, GATE start-up begins without an initial timing
cycle. The LTC4253A OV threshold is set at 5.09V with
102mV hysteresis. If OV > 5.09V, GATE pulls low. When
OV returns below 4.988V, GATE start-up begins without an
initial timing cycle. If OV occurs in the middle of an initial
timing cycle, the initial timing cycle is restarted after OV
goes away. OV does not reset the latched fault or PWRGD1
flag. The internal UVLO at VIN always overrides OV. A 1nF
to 10nF capacitor at OV prevents transients and switch-
ing noise from affecting the OV thresholds and prevents
glitches at the GATE.
UV (Pin 12): Undervoltage Input. For the LTC4253, the
thresholdattheUVpinissetat3.225Vwith0.3Vhysteresis.
If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER
pull low. If UV rises above 3.225V, this initiates an initial
timing cycle followed by GATE start-up. The LTC4253A UV
threshold is set at 3.08V with 324mV hysteresis. If UV <
2.756V, PWRGD1 pulls high, both GATE and TIMER pull
low. If UV rises above 3.08V, this initiates an initial timing
cycle followed by GATE start-up. The internal UVLO at VIN
always overrides UV. A low at UV resets an internal fault
latch. A 1nF to 10nF capacitor at UV prevents transients
and switching noise from affecting the UV thresholds and
prevents glitches at the GATE pin.
pin FuncTions
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| LTC4253AIGN#TRPBF | -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C |
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| LTC4253IGN#PBF | -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C |
| LTC4253IGN#TRPBF | -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C |
相关代理商/技术参数 |
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| LTC4253BCGN#PBF | 功能描述:IC HOT SWAP CONTROLLER 16SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 标准包装:50 系列:- 类型:热交换控制器 应用:-48V 远程电力系统，AdvancedTCA ? 系统，高可用性 内部开关:无 电流限制:可调 电源电压:11.5 V ~ 14.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽） 供应商设备封装:10-MSOP 包装:管件 |
| LTC4253BCGN#PBF | 制造商:Linear Technology 功能描述:HOT SWAP CONTROLLER -48V SSOP-16 |
| LTC4253BCGN#TRPBF | 功能描述:IC HOT SWAP CONTROLLER 16SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LTC4253BIGN#PBF | 功能描述:IC HOT SWAP CONTROLLER 16SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 标准包装:50 系列:- 类型:热交换控制器 应用:-48V 远程电力系统，AdvancedTCA ? 系统，高可用性 内部开关:无 电流限制:可调 电源电压:11.5 V ~ 14.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽） 供应商设备封装:10-MSOP 包装:管件 |
| LTC4253BIGN#PBF | 制造商:Linear Technology 功能描述:HOT SWAP CONTROLLER -48V SSOP-16 |
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