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| 型号： | LTC4259ACGW#TR |
| 厂商： | Linear Technology |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR POE QUAD AC DISC 36SSOP |
| 标准包装： | 1,000 |
| 控制器类型： | 以太网供电控制器（POE） |
| 接口： | I²C |
| 电源电压： | 3 V ~ 4 V |
| 电流 - 电源： | 2.5mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-BSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 36-SSOP |
| 包装： | 带卷 (TR) |
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LTC4259A
19
4259afb
APPLICATIO S I FOR ATIO
WU
UU
Foldback
Foldback is designed to limit power dissipation in the
MOSFET during power-up and momentary short-circuit
conditions. At low port output voltages, the voltage across
the MOSFET is high, and power dissipation will be large if
significant current is flowing. Foldback monitors the port
output voltage and reduces the VLIM current limit level
linearly from its full value (212.5mV typ) at a port voltage
of 18V to approximately 1/7th of the full value (30mV typ)
at a port voltage of 0V. With 0.5
sense resistors, this
limits the short-circuit current to 60mA (typ) instead of the
full 425mA (typ) current limit. When the LTC4259A is in
foldback, the tICUT timer is active.
Short-Circuit Protection
If a port is suddenly shorted out, the MOSFET power
dissipation can rise to very high levels, jeopardizing the
MOSFET even before the normal current limit circuit can
respond. A separate short-circuit current limit circuit
watches for significant overcurrent events (VSENSE
>275mV, >550mA with a 0.5
sense resistor) and pulls
the GATE pin down immediately if such an event occurs,
shutting off the MOSFET in less than 1
s (with no external
capacitor on GATE). Approximately 100
s later, GATE is
allowed to rise back up and the normal current limit circuit
will take over, allowing ILIM current to flow and causing the
tICUT timer to count up. During a short circuit, ILIM will be
reduced by the foldback feature to 1/7th of the nominal
value.
Choosing External MOSFETs
Power delivery to the ports is regulated with external
power MOSFETs. These MOSFETs are controlled as previ-
ously described to meet the IEEE 802.3af specification.
Under normal operation, once the port is powered and the
PD’s bypass capacitor is charged to the port voltage, the
external MOSFET dissipates very little power. This sug-
gests that a small MOSFET is adequate for the job. Unfor-
tunately, other requirements of the IEEE 802.3af mandate
a MOSFET capable of dissipating significant power. When
the port is being powered up, the port voltage must reach
30V or more before the PD turns on. The port voltage can
then drop to 0V as the PD’s bypass capacitor is charged.
According to the IEEE, the PD can directly connect a 180
F
capacitor to the port and the PSE must charge that
capacitor with a current limit of 400mA to 450mA for at
least 50ms.
An even more extreme example is a noncompliant PD that
provides the proper signature during detection but then
behaves like a low valued resistor, say 50
,inparallelwith
a 1
F capacitor. When the PSE has charged this
noncompliant PD up to 20V, the 50
resistor will draw
400mA (the minimum IEEE prescribed ILIM current limit)
keeping the port voltage at 20V for the remainder of tSTART.
The external MOSFET sees 24V to 37V VDS at 400mA to
450mA, dissipating 9.6W to 16.7W for 60ms (typ).
The LTC4259A implements foldback to reduce the current
limit when the MOSFET VDS is high; see the Foldback
section. Without foldback, the MOSFET could see as much
as 25.7W for 60ms (typ) when powering a shorted or a
250ns/DIV
4258 G04
GND
PORT
VOLTAGE
20V/DIV
GATE
VOLTAGE
10V/DIV
PORT
CURRENT
20A/DIV
VEE
+15V
VDD = 3.3V
VEE = –48V
VEE
0mA
SHORT APPLIED
FET OFF
FAST PULL-DOWN
ACTIVATED
100
s/DIV
4258 G05
PORT
VOLTAGE
20V/DIV
GATE
VOLTAGE
10V/DIV
PORT
CURRENT
500mA/DIV
VDD = 3.3V
VEE = –48V
VEE
GND
0mA
CURRENT LIMIT
SHORT APPLIED
SHORT REMOVED
FAST PULL-DOWN
VEE
+15V
Figure 15. Rapid Response to 1
Short
Figure 16. Rapid Response to Momentary 100
Short
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