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参数资料
| 型号： | LTC4414IMS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR POWERPATH 8-MSOP |
| 标准包装： | 50 |
| 系列： | PowerPath™ |
| 应用： | 电池备份，工业/汽车，大电流开关 |
| FET 型： | P 沟道 |
| 输出数： | 1 |
| 内部开关： | 无 |
| 延迟时间 - 开启： | 600µs |
| 延迟时间 - 关闭： | 20µs |
| 电源电压： | 3 V ~ 36 V |
| 电流 - 电源： | 33µA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
LTC4414
APPLICATIO S I FOR ATIO
way to avoid unwanted I ? R drops in the power path. Both
pins are protected from negative voltages.
GATE Pin Usage
The GATE pin controls the external P-channel MOSFET
connected between the V IN and SENSE pins when the load
current is supplied by the power source at V IN . In this
mode of operation, the internal current source, which is
responsible for pulling the GATE pin up, is limited to a few
microamps (I G(SRC) ). If external opposing leakage cur-
rents exceed this, the GATE pin voltage will reach the
clamp voltage (V GON ) and V DS will be smaller. The internal
current sink, which is responsible for pulling the GATE pin
down, has a higher current capability (I G(SNK) ). With an
auxiliary supply input pulling up on the SENSE pin and
exceeding the V IN pin voltage by 20mV (V RTO ), the device
enters the reverse turn-off mode and a much stronger
current source is available to oppose external leakage
currents and turn off the MOSFET (V GOFF ).
While in forward regulation, if the on resistance of the
MOSFET is too high to maintain forward regulation, the
GATE pin will maximize the MOSFET’s V GS to that of the
clamp voltage (V GON ). The clamping action takes place
between V IN and the GATE pin.
STAT Pin Usage
During normal operation, the open-drain STAT pin can be
biased at any voltage between ground and 36V regardless
of the supply voltage to the LTC4414. It is usually con-
nected to a resistor whose other end connects to a voltage
source. In the forward regulation mode, the STAT pin will
be open (I S(OFF) ). When a wall adaptor input or other
auxiliary supply is connected to that input, and the voltage
on SENSE is higher than V IN + 20mV (V RTO ), the system is
in the reverse turn-off mode. During this mode of opera-
tion the STAT pin will sink at least 50 μ A of current
(I S(SNK) ). This will result in a voltage change across the
resistor, depending on the resistance, which is useful to
turn on an auxiliary P-channel MOSFET or signal to a
microcontroller that an auxiliary power source is con-
CTL Pin Usage
This is a digital control input pin with low threshold
voltages (V IL, V IH ) for use with logic powered from as little
as 1V. During normal operation, the CTL pin can be biased
at any voltage between ground and 36V, regardless of the
supply voltage to the LTC4414. A logical high input on this
pin forces the gate to source voltage of the primary
P-channel MOSFET power switch to a small voltage (V GOFF ).
This will turn the MOSFET off and no current will flow from
the primary power input at V IN if the MOSFET is configured
so that the drain to source diode is not forward biased. The
high input also forces the STAT pin to sink at least 50 μ A of
current (I S(SNK) ). See the Typical Applications for various
examples on using the STAT pin. A 3.5 μ A internal pull-
down current (I CTL ) on the CTL pin will insure a logical low
level input if the pin should be open.
Protection
Most of the application circuits shown provide some
protection against supply faults such as shorted, low or
reversed supply inputs. The fault protection does not
protect shorted supplies but can isolate other supplies and
the load from faults. A necessary condition of this protec-
tion is for all components to have sufficient breakdown
voltages. In some cases, if protection of the auxiliary input
(sometimes referred to as the wall adapter input) is not
required, then the series diode or MOSFET may be
eliminated.
Internal protection for the LTC4414 is provided to prevent
damaging pin currents and excessive internal self heating
during a fault condition. These fault conditions can be a
result of V IN , SENSE, GATE or CTL pins shorted to ground
or to a power source that is within the pin’s absolute
maximum voltage limits. Both the V IN and SENSE pins are
capable of being taken significantly below ground without
current drain or damage to the IC (see Absolute Maximum
Voltage Limits). This feature allows for limited reverse-
battery condition without current drain or damage. This
internal protection is not designed to prevent overcurrent
or overheating of external components.
nected. External leakage currents, if significant, should be
accounted for when determining the voltage across the
resistor when the STAT pin is either on or off.
4414fc
8
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