参数资料
| 型号： | LV5768M-TLM-H |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM MFP14S |
| 标准包装： | 1,000 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 95% |
| 电源电压： | 8.5 V ~ 42 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | * |
| 包装： | * |
LV5768M
The equation (9) becomes
Vref
VO
× GMEA × RC ×
RL
1+2 π × fZC × CO × RL
=1
(11)
From the equation, phase compensation external resistor RC is obtained by the following formula. However,
GCS=0.67/Rdson=29A/V, GMEA=1400μA/V.
Given that output is 12V and load resistor is 1.7 ? (7A load):
VO
∴ RC = Vref × G
1
MEA
× G
1
CS
×
1+2 π × fZC × CO × RL
RL
(12)
= 0.67 × 1400μA/V × 29A/V ×
≈ 39k ?
12 1 1
1+2 × 3.14 × 10k × 1410μ × 1.7
1.7
(13)
This is the external resistor value RC obtained from this calculation (the calculation reveals that the last block where
load resistor RL is inserted is 1 ? 2 π × fZC × CO × RL. Therefore, there is no need for depending RL.).
When point zero fZ (6) and pole fp1 (5) are the same values, they cancel out each other. Hence, there is only one pole
frequency for the phase characteristics of closed loop gain. In other words, you can obtain characteristics in which
waveform is stable because the gain frequency lowers at -20dB/DEC and phase only rotates by -90 degree.
Since (6) = (5) fZ = fp1
(14)
1
2 π CORC
=
1
2 π CORL
∴ CC =
RL × CO
RC
=
1.7 × 1410μ
39k
= 0.062μF
The external constant between phase compensator pin COMP and GND is obtained as such using ideal equations. In
reality, stable phase constant should be defined based on testing under the entire temperature, load and input voltage
range. On the other hand, such ideal value is used as starting point for the assessment. In the deliverable evaluation
board, the above constants are used as initial value. CC and RC are defined according to conditions of transient
response. If the influence of noise is significant, it is advisable to increase constant than the CC value.
7) Input capacitor selection
When switching of the IC occurs, ripple current flows into the input-side capacitor of DC-DC converter. Like input
current, the more the output current flows, the more the ripple current into input side capacitor flows. Also, the lower
the input voltage is, the more the duty expands. As a result, the ripple current flows more. Allow higher ripple
current than the result of the equation. The capacitor of input side should be connected adjacent to the power IC and
minimize the inductance from the pattern layout. Execution value is obtained by the equation (15).
Irip_in =
D ( 1 ? D ) × IOUT [Arms]
(15)
D represents duty cycle defined by VOUT/VIN.
8) Output capacitor selection
If ceramic capacitor is used to output, output ripple voltage is obtained as follows since the capacitance of ESR is
small.
Vrip =
VOUT
8 × L × CO × fOSC
2 × (1-
VOUT
VIN ) [V]
(16)
Also if electrolytic capacitor is used to output, output ripple voltage is affected by ESR since the capacitance of ESR
is large. In this case, output ripple voltage is obtained by the following equation.
Vrip =
VIN - VOUT
fOSC × VIN
×
VOUT × RC
L
[V]
(17)
Since the allowable ripple current of electrolytic capacitor is lower compared to that of ceramic capacitor, the
allowable ripple current value must not be exceeded. Execution value is obtained by the following equation.
PS No.A1988-11/15
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