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| 型号： | M-ORT82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 6/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G51BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
14
Transmit Path (FPGA → Backplane) Logic
The transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel interface to the
FPGA logic. It also uses the reference clock, REFCLK[P:N]_[A:B] to synthesize an internal high-speed serial bit
clock. The serialized transmitted data are available at the differential CML output pins to drive either an optical
transmitters, coaxial media or a circuit board backplane.
As shown in Figure 3, the basic blocks in the transmit path include:
Embedded Core/FPGA interface and 4:1 multiplexer
Low speed parallel core/FPGA interface
4:1 multiplexer
Transmit SERDES
8b/10b Encoder
10:1 Multiplexer
CML Output Buffer
Pseudo-Random Bit Sequence (PRBS) Generator and Checker
Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock dis-
tribution, including the transmit PLL, and of the Pseudo-Random Bit Sequence (PRBS) generator are given in later
sections of this data sheet.
Figure 3. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)
Embedded Core/FPGA Logic Interface and 4:1 Multiplexer
These blocks provide the data formatting and transmit data and clock signal transfers between the Embedded Core
and the FPGA Logic. Control and status registers in the FPGA portion of the chip contain to control the transmit
÷ 4
FIFO
4:1 MUX
(x9)
PLL
PRBS
Gen.
CML
Buffer
with Pre-
emphasis
10:1
MUX
8B/10B
Encoder
(with
bypass)
Interface and MUX Block
TX SERDES Block
STBD_xx[7:0]
STBD_xx[8]
STBD_xx[9]
STBC311_xx
8
8-bit data
K-control
Force-ve disparity
312.5 MHz
HDOUTP_xx
HDOUTN_xx
REFCLKP_[A:B]
REFCLKN_[A:B]
CML
Buffer
Backplane
Serial
Link
FPGA
Logic
TWDxx[31:0]
32
TCOMMAxx[3:0]
4
TBIT9xx[3:0]
4
TSYS_CLK_xx
MUX
TCK78[A:B]
78.125 MHz
TCKSEL[0:1][A:B]
Logic Common to Quad
From other 3
channels
To other 3
channels
From Control
Register
{
Note: xx= [AA, AB, ... BD]
156.25 MHz
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