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参数资料
| 型号： | M28W320FSB |
| 厂商： | 意法半导体 |
| 英文描述： | 32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Boot Block, Secure Flash Memories |
| 中文描述： | 32兆（含2Mb × 16）和64Mbit（4Mb的x16）的3V电源，启动块，安全闪存 |
| 文件页数： | 4/45页 |
| 文件大小： | 299K |
| 代理商： | M28W320FSB |
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M28W320EBT, M28W320EBB
12/45
Erase aborts if Reset turns to VIL. As data integrity
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will only ac-
cept the Read Status Register command and the
Program/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 7, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See Appendix C, Figure 20, Erase Flowchart and
Pseudo Code, for the flowchart for using the Erase
command.
Program Command
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program command.
s
The first bus cycle sets up the Program
command.
s
The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
During Program operations the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Program times
are given in Table 7, Program, Erase Times and
Program/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix C, Figure 16, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0. Programming should not be attempt-
ed when VPP is not at VPPH.
Three bus write cycles are necessary to issue the
Double Word Program command.
s
The first bus cycle sets up the Double Word
Program command.
s
The second bus cycle latches the Address and
the Data of the first word to be written.
s
The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to VIL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 17, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using
the
Double Word Program
command.
Quadruple Word Program Command
This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when VPP is not at VPPH.
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
s
The first bus cycle sets up the Quadruple Word
Program Command.
s
The second bus cycle latches the Address and
the Data of the first word to be written.
s
The third bus cycle latches the Address and the
Data of the second word to be written.
s
The fourth bus cycle latches the Address and
the Data of the third word to be written.
s
The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to VIL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 18, Quadruple Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Quadruple Word Program
command.
Clear Status Register Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase control-
ler.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron-
ic Signature and Read CFI Query commands. Ad-
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