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参数资料
| 型号： | M34571GD-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封装： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件页数： | 25/33页 |
| 文件大小： | 1526K |
| 代理商： | M34571GD-XXXFP |
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Rev.1.02
May 25, 2007
Page 29 of 124
REJ03B0179-0102
4571 Group
Fig 32. Timers structure (2)
Watchdog reset
signal
reset signal
(Note 3)
D
T
Q
R
DWDT instruction
+
WRST instruction
Reset signal
(Note 4)
(Note 2)
WRST instruction
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
INSTCK
S
R
Q
WDF1
S
R
Q
WEF
C/CNTR1
Port C output
PWMOUT
PWMOD
W12
W51
Q
R
D
T
T1UDF
W30
0
1
XIN
W31
Timer 3 (8)
Reload Register R3L (8)
Register B
(TAB3)
(T3AB)
Register A
(T3AB)
(TAB3)
(T3R3L)
Reload control circuit
(Note 1)
Reload Register R3H (8)
(T3HAB)
Register B
Register A
W33
Timer 3
interrupt
1/2
ORCLK
TQ
R
W32
1
0
“H” interval expansion
T3F
PWMOD
T2UDF: Timer 2 underflow signal
ORCLK: Prescaler output
Note 1: When the CNTR1 output function is valid (W33=“1”), the value is auto-reloaded alternately from reload register
R3L and R3H every timer 3 underflow.
When the CNTR1 function is invalid (W33=“0”), the value is auto-reloaded from reload register R3L only.
2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
4: The WEF flag is set to “1” at system reset or RAM back-up mode.
Data is set automatically from each reload register
when timer underflows (auto-reload function).
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