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参数资料
| 型号： | M34571GD-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封装： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件页数： | 6/33页 |
| 文件大小： | 1526K |
| 代理商： | M34571GD-XXXFP |
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Rev.1.02
May 25, 2007
Page 12 of 124
REJ03B0179-0102
4571 Group
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as
4-bit data addition, comparison, AND operation, OR operation,
and bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 7).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 8).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and register
A as the low-order 4 bits (Figure 9).
Register E is undefined after system is released from reset and
returned from the RAM back-up. Accordingly, set the initial
value.
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A
and is used as a pointer within the specified page when the TABP
p, BLA p, or BMLA p instruction is executed (Figure 10).
Also, when the TABP p instruction is executed at UPTF flag =
“1”, the high-order 2 bits of ROM reference data is stored to the
low-order 2 bits of register D, the high-order 1 bit of register D is
“0”.
When the TABP p instruction is executed at UPTF flag = “0”, the
contents of register D remains unchanged. The UPTF flag is set
to “1” with the SUPT instruction and cleared to “0” with the
RUPT instruction.
The initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and
returned from the RAM back-up. Accordingly, set the initial
value.
Fig 7.
AMC instruction execution example
Fig 8.
RAR instruction execution example
Fig 9.
Registers A, B and register E
Fig 10. TABP p instruction execution example
(CY)
<Result>
(M(DP))
(A)
Addition
ALU
<Carry>
<Clear>
RC instruction
<Set>
SC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
A3 A2 A1 A0
Register A
TAB instruction
E3 E2 E1 E0
E7 E6 E5 E4
B3 B2 B1 B0
Register B
TEAB instruction
Register E
A3 A2 A1 A0
Register A
TBA instruction
B3 B2 B1 B0
Register B
TABE instruction
A3 A2 A1 A0
DR2 DR1 DR0
PCL
Register A (4)
Low-order 4bits
Register D (3)
High-order 2 bits
Register B (4)
Middle-order 4 bits
ROM
Immediate field
value p
The contents of
register D
The contents of
register A
Specifying address
TABP p instruction
* Flag UPTF = 1;
High-order 2 bits of reference data is transferred to
the low-order 2 bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
p3
p2
p1
p0
p6
p5
p4
PCH
840
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