
Rev.3.00
2004.08.06
page 79 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FR03
FR02
FR01
FR00
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Ports P12, P13 output structure selection
bit
Ports P10, P11 output structure selection
bit
Ports P02, P03 output structure selection
bit
Ports P00, P01 output structure selection
bit
Port output structure control register FR0
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
FR13
FR12
FR11
FR10
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Port D3 output structure selection bit
Port D2 output structure selection bit
Port D1 output structure selection bit
Port D0 output structure selection bit
Port output structure control register FR1
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
FR23
FR22
FR21
FR20
This bit has no function, but write is enabled.
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Not used
Port D6/CNTR0 output structure selection bit
Port D5 output structure selection bit
Port D4 output structure selection bit
Port output structure control register FR2
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.
W
TFR0A
W
TFR1A
W
TFR2A
FR33
FR32
FR31
FR30
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Port P53 output structure selection bit
Port P52 output structure selection bit
Port P51 output structure selection bit
Port P50 output structure selection bit
Port output structure control register FR3
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
W
TFR3A
8-bit general-purpose register SI
at reset : undefined
at RAM back-up : undefined
R/W
8-bit general purpose register.
8-bit data can be transferred between register A and register B with the TABSI and TSIAB instructions.