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参数资料
型号： M34584EDFP
元件分类： 微控制器/微处理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
封装： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件页数： 75/157页
文件大小： 1130K
代理商： M34584EDFP
Rev.3.00
2004.08.06
page 24 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Interrupt control register V2
The timer 3, timer 4 and A/D interrupt enable bit is assigned to
register V2. Set the contents of this register through register A
with the TV2A instruction. The TAV2 instruction can be used to
transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are sat-
isfied on execution of other than one-cycle instructions (Refer to
Figure 16).
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V13
V12
V11
V10
V23
V22
V21
V20
Not used
A/D interrupt enable bit
Timer 4 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V2
at RAM back-up : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
at RAM back-up : 00002
at reset : 00002
R/W
TAV1/TV1A
R/W
TAV2/TV2A
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