参数资料
型号: M34D64-WDW6T
厂商: 意法半导体
元件分类: DRAM
英文描述: 64 Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Quarter of Memory
中文描述: 64千位串行I2C总线的EEPROM,带有硬件写控制记忆的热门季
文件页数: 14/21页
文件大小: 147K
代理商: M34D64-WDW6T
M34D64
14/21
Table 13. AC Characteristics (M34D64-W)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. The Write Time of 5 ms only applies to devices bearing the process identification letter "B" in the package marking (on the top side
of the pack-age), otherwise (for devices bearing the process identification letter "N") the Write Time is 10 ms. For further details,
please contact your nearest ST sales office.
Test conditions specified in Table 9 and Table 7
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
CH1CH2
t
R
Clock Rise Time
300
ns
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2 2
t
R
SDA Rise Time
20
300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
5 or
4
10
ms
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