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参数资料
| 型号： | M37544G2SP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件页数： | 20/68页 |
| 文件大小： | 738K |
| 代理商： | M37544G2SP |
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7544 Group
Rev.1.04
2004.06.08
page 27 of 66
REJ03B0012-0104Z
Fig. 28 Block diagram of clock synchronous serial I/O
Fig. 29 Operation of clock synchronous serial I/O function
Serial I/O
●Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6)
to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
1/4
F/F
P12/SCLK
Serial I/O status register
Serial I/O control register
P13/SRDY
P10/RXD
P11/TXD
XIN
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus
Address 001816
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit shift register
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY
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