参数资料
型号: M37545G4-XXXGP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件页数: 21/65页
文件大小: 782K
代理商: M37545G4-XXXGP
Rev.1.07
Mar 19, 2009
Page 26 of 60
REJ03B0140-0107
7545 Group
Timers
The 7545 Group has 3 timers: timer 1, timer 2 and timer 3.
The division ratio of every timer and prescaler is 1/(n+1)
provided that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”,
a n underfl o w occurs at the n e xt co un t pu lse, and the
corresponding timer latch is reloaded into the timer. When a
timer underflows, the interrupt request bit corresponding to each
timer is set to “1”.
1. Timer 1
Timer 1 is an 8-bit timer and counts the prescaler 1 output.
When Timer 1 underflows, the timer 1 interrupt request bit is set
to “1”.
Prescaler 1 is an 8-bit prescaler and counts the clock which is
f(XIN) divided by 16.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when
Timer 1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is
written to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is
executed, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the clock which is f(XIN) divided by 16. Each
time the count clock is input, the contents of Prescaler 1 is
decremented by 1. When the contents of Prescaler 1 reach
“0016”, an underflow occurs at the next count clock, and the
prescaler 1 latch is reloaded into Prescaler 1 and count continues.
The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
Timer 1 counts the underflow signal of Prescaler 1. The contents
of Timer 1 is decremented by 1 each time the count clock is
input.
When the contents of Timer 1 reach “0016”, an underflow occurs
at the next count clock, and the timer 1 latch is reloaded into
Timer 1 and count continues. The division ratio of Timer 1 is
1/(m+1) provided that the value of Timer 1 is m.
Timer 1 is stopped by setting “1” to the timer 1 count stop bit.
2. Timer 2
Timer 2 is an 8-bit timer and counts the clock selected by the
timer 2 count source selection bit. When Timer 2 underflows, the
timer 2 interrupt request bit is set to “1”.
Timer 2 has two timer latches (primary latch and secondary
latch) to retain the reload value.
The value written to timer 2 primary (T2P) while timer 2 is
stopped is transferred to the timer 2 primary latch and the
counter.
The value written to timer 2 secondary (T2S) while timer 2 is
stopped is transferred only to timer 2 secondary latch.
After the count of timer 2 starts, the values written to timer 2
primary (T2P) and timer 2 secondary (T2S) are transferred only
to each latch. The values are not transferred to the counter at
write.
When each timer underflows, the values of timer 2 primary latch
and the timer 2 secondary latch are alternately transferred to the
counter. (Since a count value of a timer is retained, the written
value becomes the count value of the timer after the next
underflow.)
When timer 2 primary (T2P) is read, the count value of the timer
is read. When timer 2 secondary (T2S) is read, a set value of
timer 2 secondary is read. (Read the timer 2 primary to read the
count value even during the count period of timer 2 secondary.)
When the timer 2 primary is read, the count value of timer 2 is
read since the count value of the timer 2 is retained until writing
to timer 2 primary (T2P) is performed after timer 2 is stopped.
Timer 2 always operates in the timer mode.
Timer 2 counts the clock selected by the timer 2 count source
selection bit. The contents of Timer 2 is decremented by 1 each
time the count clock is input. When the contents of Timer 2 reach
“0016”, an underflow occurs at the next count clock, and the
timer 2 primary latch or timer 2 secondary latch is alternately
reloaded into Timer 2 and count continues.
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