
SERIAL I/O
7702/7703 Group User’s Manual
7–33
[Precautions when operating in clock synchronous serial I/O mode]
1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when
performing only reception, transmit operation (setting for transmission) must be performed. In this case,
dummy data is output from the TxDi pin.
2. When an internal clock is selected during reception, the transfer clock is generated by setting the transmit
enable bit to “1” (transmission enabled) and setting dummy data to the UARTi transmission buffer register.
When an external clock is selected , the transfer clock is generated by setting the transmit enable bit to
“1” and inputting a clock to the CLKi pin after setting dummy data to the UARTi transmission buffer
register.
3. When selecting an external clock, satisfy the following 3 conditions with the input to CLKi pin = “H” level.
<When transmitting>
Set the transmit enable bit to “1.”
Write transmit data to the UARTi transmit buffer register.
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Input “L” level to the CTSi pin (when selecting the CTS function).
<When receiving>
Set the receive enable bit to “1.”
Set the transmit enable bit to “1.”
Write dummy data to the UARTi transmit buffer register.
4. When receiving data, write dummy data to the low-oreder byte of the UARTi transmission buffer register
for each reception of 1-byte data.
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5. The output level of the RTSi pin becomes “L” simultaneously at setting the receive enable bit to “1.” The
output level of this pin becomes “H” when receive starts, and it becomes “L” when receive is completed.
The output level of this pin changes regardless of the contents of the transmit enable bit, the transmission
buffer empty flag, and the receive complete flag.
7.3 Clock synchronous serial I/O mode