
RESET
7702/7703 Group User’s Manual
13–8
13.1 Hardware reset
Fig. 13.1.6 State of SFR and internal RAM areas immediately after reset (4)
UART1 receive interrupt control register
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
6B16
6C16
6D16
6E16
6F16
6A16
Address
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART1 transmit interrupt control register
INT2 interrupt control register
Watchdog timer frequency select register
Register name
Watchdog timer register
Timer A0 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
Access characteristics
RW
b7
b0
RW
State immediately after a reset
0
?(Note 2)
b7
b0
UART0 receive interrupt control register
Timer A1 interrupt control register
Timer B0 interrupt control register
INT1 interrupt control register
0
00
0
By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer.
The dummy data is not retained anywhere.
The value “FFF16” is set to the watchdog timer. (Refer to “Chapter 9. WATCHDOG TIMER.”)
qInternal RAM area; addresses 8016 to 27F16 in M37702M2BXXXFP)
At hardware reset
(Except the case that Stop or Wait mode is terminated)...............................................
Undefined.
At software reset..........................................................Retaining the state immediately before a reset
At terminating Stop or Wait mode
(Hardware reset is used to terminate it)...............Retaining the state immediately before the STP or
WIT instruction is executed
RW
Notes 1:
2:
(Note 1)
?
(Note 3)
?
RW
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
?
0
00
0
00
0
00
0
?
0
00