参数资料
型号: M38C29FFAFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP64
封装: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件页数: 4/104页
文件大小: 1327K
代理商: M38C29FFAFP
Rev.2.00
May 28, 2004
page 99 of 100
38C2 Group (A Version)
Notes on LCD Drive Control Circuit
1. Count source for LCDCK
The LCDCK count source selection bit (bit 7 of LCD mode register
(address 003916)) is set to “0” after reset, selecting f(XCIN)/32. The
sub clock has stopped after reset. Therefore, turn on LCD after start-
ing the oscillation and stabilizing the oscillation. Select the LCDCK
count source after the corresponding clock source becomes stable.
2. STP instruction
When executing the STP instruction, bits 0 to 5 and bit 7 of the LCD
power supply control register and the LCD enable bit (bit 3 of LCD
mode register) are set to “0”. Set these bits again after returning from
stop mode.
3. When not using LCD
When not using an LCD, leave the LCD segment and common pins
open. Connect the VL1 pin to Vss, and the VL2 and VL3 pins to Vcc.
4. LCD drive power supply
(1) Power supply capacitor may be insufficient with the division resis-
tance for LCD power supply, and the characteristic of the LCD
panel. In this case, there is the method of connecting the bypass
capacitor about 0.1–0.33
F to VL1–VL3 pins. The example of a
strengthening measure of the LCD drive power supply is shown
in Figure 9.
VL3
VL2
VL1
Connect by the shortest possible wiring.
Connect the bypass capacitor to the VL1– VL3 pins
as short as possible.
(Referential value: 0.1– 0.33
F)
38C2 group
(A version)
Fig. 9 Strengthening measure example of LCD drive power
supply
(2) When the LCD drive control circuit is used at VL3 = VCC, apply
VCC to VL3 pin and write “1” to VL3 connection bit (bit 6 of the LCD
power control register (address 003816)).
(3) When the voltage is applied to VL1 to VL3 by using the external
resistor, write “102” to dividing resistor for LCD power selection
bits (RSEL) of the LCD power control register (address 003816).
5. Segment output disable register
(1) Only pins set to output ports by the direction register can be con-
trolled to switch to output ports or segment outputs by the seg-
ment output disable register.
(2) When the VL pin input selection bit (VLSEL) of the LCD power
control register (address 003816) is “1”, settings of the segment
output disable bit 22 and segment output disable bit 23 are invalid.
6. Data setting to LCD display RAM
When writing a data into the LCD display RAM during LCD being
turned ON (LCD enable bit = “1”), write the confirmed data. Do not
write temporarily on the LCD display RAM because this might cause
the LCD display flickering. Figure 10 shows the write procedure for
LCD display RAM when LCD is on.
Fig. 10 Write procedure for LCD display RAM when LCD is on
Notes on Watchdog Timer
1. The watchdog timer is operating during the wait mode. Write data
to the watchdog timer control register to prevent timer underflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the wait time (time set by timer 1
and timer 2) and the watchdog timer control register must be writ-
ten just before executing the STP instruction.
3. The count source of the watchdog timer is affected by the system
clock
φ selected by the system clock selection bits (bits 6, 7 of
CPU mode register (address 003B16)).
(1)Right process example
LCD
ON
LCD
ON
or
OFF
Sets determinate data to
LCD display RAM
Sets LCD display RAM data
LRAM0 (Address : 4016)
← “ FF
16
LCD display
ON or OFF ?
Sets turn off data to LCD display RAM
Sets determinate
data to LCD diplay
RAM
(2) Error process example
LCD
ON
LCD
ON
or
OFF
LCD
OFF
ON
Contents of addres 004016 are “ FF
16
LCD display
ON or OFF ?
Sets LCD display RAM data
LRAM0 (Address : 4016)
← “ FF
16
Sets LCD display RAM data
LRAM0 (Address : 4016)
← “ 00
16
Sets LCD display RAM data
LRAM0 (Address : 4016)
← “ 00
16
Contents of addres 004016 are “ FF
16
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