参数资料
型号: M38D5XGXHP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP80
封装: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件页数: 10/142页
文件大小: 2004K
代理商: M38D5XGXHP
Rev.3.04
May 20, 2008
Page 107 of 134
REJ03B0158-0304
38D5 Group
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0”.
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0”.
Fig 95. Circuit for measuring output switching characteristics
Table 32
Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta =
20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ
Max.
tWH(SCLK1)
Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2-30
ns
tWL(SCLK1)
Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2-30
ns
td(SCLK1-TxD)
Serial I/O1 output delay time (1)
140
ns
tv(SCLK1-TxD)
Serial I/O1 output valid time (1)
30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
30
ns
tf(SCLK1)
Serial I/O1 clock output falling time
30
ns
tWH(SCLK2)
Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2-30
ns
tWL(SCLK2)
Serial I/O2 clock output “L” pulse width
tc(SCLK2)/2-30
ns
tf(SCLK2)
Serial I/O2 clock output falling time
40
ns
td(SCLK2-SOUT2)
Serial I/O2 output delay time
140
ns
tv(SCLK2-SOUT2)
Serial I/O2 output valid time
30
ns
Table 33
Switching characteristics (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta =
20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ
Max.
tWH(SCLK1)
Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2-80
ns
tWL(SCLK1)
Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2-80
ns
td(SCLK1-TxD)
Serial I/O1 output delay time (1)
350
ns
tv(SCLK1-TxD)
Serial I/O1 output valid time (1)
-30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
80
ns
tf(SCLK1)
Serial I/O1 clock output falling time
80
ns
tWH(SCLK2)
Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2-80
ns
tWL(SCLK2)
Serial I/O2 clock output “L” pulse width
tc(SCLK2)/2-80
ns
tf(SCLK2)
Serial I/O2 clock output falling time
80
ns
td(SCLK2-SOUT2)
Serial I/O2 output delay time
350
ns
tv(SCLK2-SOUT2)
Serial I/O2 output valid time
-30
ns
Measurement output pin
100pF
CMOS output
Measurement output pin
100pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1.”
(N-channel open-drain output mode)
1k
QzROM VERSION
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