
Rev.3.04
May 20, 2008
REJ03B0158-0304
38D5 Group
Fig. 19 Structure of interrupt-related registers
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Key input interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt request register 1
(IREQ1 : address 003C16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Key input interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive/transmit interrupt request bit
CNTR0 interrupt request bit
Timer Y interrupt request bit
CNTR1 interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
Timer 4 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive/transmit interrupt enable bit
CNTR0 interrupt enable bit
Timer Y interrupt enable bit
CNTR1 interrupt enable bit
AD conversion interrupt enable bit
Not used (do not write to “1”)
Interrupt control register 2
(ICON2 : address 003F16)
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt control register 1
(ICON1 : address 003E16)
Interrupt request register 2
(IREQ2 : address 003D16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
Timer Y/CNTR1 interrupt switch bit
0 : Timer Y interrupt
1 : CNTR1 interrupt
INT0 input port switch bit
0 : input from Port P62 (INT00)
1 : input from Port P70 (INT01)
INT1 input port switch bit
0 : input from Port P66 (INT10)
1 : input from Port P71 (INT11)
Not used (do not write to “1”)
Not used (return “0” when read)
Interrupt edge selection register
(INTEDGE : address 003A16)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0