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参数资料
| 型号： | M41ST87YWX6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封装： | 0.300 INCH, PLASTIC, SO-28 |
| 文件页数： | 15/38页 |
| 文件大小： | 569K |
| 代理商： | M41ST87YWX6 |
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M41ST87Y, M41ST87W
22/38
Tamper Detection Operation
The Tamper Pins are triggered based on the state
of an external switch. Two switch mode options
are available, “Normally Open” or “Normally
Closed,” based on the setting of the Tamper Con-
nect Mode Bit (TCMX). If the selected switch mode
is Normally Open (TCMX = '1'), the Tamper Pin will
be triggered by being connected to VSS (if the
TPMX Bit is set to '0') or to VCC (if the TPMX Bit is
set to '1'), through the closing of the external
switch. When the external switch is closed, the
Tamper Bit will be immediately set, allowing the
user to determine if the device has been physically
tampered with. If the selected switch mode is Nor-
mally Closed (TCMX = '0'), the Tamper Pin will be
triggered by being pulled to VSS or to VOUT (de-
pending on the state of the TPMX Bit), through an
internal pull-up/pull-down resistor as a result of
opening the external switch.
When a tamper event occurs, the Tamper Bits
(TB1 and/or TB2) will be immediately set if TEBX =
'1.'
If the Tamper Interrupt Enable Bit (TIEX) is set to a
'1,' the IRQ/OUT pin will also be activated. The
IRQ/OUT output is cleared by a READ of the Flags
Register (as seen in Figure 23, page 27), a reset
of the TIE Bit to '0,' or the RST output is enabled.
Note: In order to avoid an inadvertent activation of
the IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to reset-
ting the TEBX Bit.
The Tamper Bits are “Read only” bits and are reset
only by writing the Tamper Enable Bit (TEBX) to '0.'
The Tamper Detect function operates both under
normal power, and in battery back-up. Even if the
trigger event occurs during a power-down condi-
tion, the bit will be set correctly.
Sampling
As the Switch Mode Normally Closed (TCMX ='0')
requires a greater amount of current to maintain
constant monitoring, the M41ST87Y/W offers a
programmable
Tamper
Detect
Sampling
Bit
(TDSX) to reduce the current drawn on VCC or
sampling frequency is once per second (1Hz), for
approximately 1ms.
When TEBX is disabled, no current will be drawn
by the Tamper Detection Circuit. After a tamper
event has been detected, no additional current will
be drawn.
Note: The oscillator must be running for Tamper
Detection to operate in the sampling mode. If the
oscillator is stopped, the Tamper Detection Circuit
will revert to constant monitoring.
Note: Sampling in the Tamper High Mode
(TPMX = '1') may be bypassed while on VCC by
connecting the TPXIN pin to VCC through an exter-
nal resistor. This will allow constant monitoring
when VCC is “On” and revert to sampling when in
battery back-up (see Figure 15, page 16).
Internal Tamper Pull-up/down Current
Depending on the capacitive and resistive loading
of the Tamper Pin Input (TPXIN), the user may re-
quire more or less current from the internal pull-up/
down used when monitoring the Normally Closed
switch mode. The state of the Tamper Current Hi/
Tamper Current Low Bit (TCHI/TCLOX) deter-
mines the sizing of the internal pull-up/-down.
TCHI/TCLOX = '1' uses a 1M pull-up/-down re-
sistor, while TCHI/TCLOX = '0' uses a 10M pull-
up/-down resistor (see Figure 19, page 19).
Note: No additional, external capacitance is re-
quired on the Tamper Input pin.
Tamper Event Time-Stamp
Regardless of which tamper occurs first, not only
will the appropriate Tamper Bit be set, but the
event will also be automatically time-stamped.
This is accomplished by freezing the normal up-
date of the clock registers (00h through 07h) im-
mediately following a tamper event. Thus, when
tampering occurs, the user may first read the time
registers to determine exactly when the tamper
event occurred, then re-enable the clock update to
the current time (and reset the Tamper Bit, TBX) by
resetting the Tamper Enable Bit (TEBX).
The time update will then resume and the clock
can be read to determine the current time. Both
Tamper Enable Bits (TEBX) must always be set to
'0' in order to read the current time.
In the event of multiple tampers, the Time-Stamp
will reflect the initial tamper event.
Note: If the TEBX Bit is set, the Tamper Event
Time-Stamp will take precedence over the Power
Down Time-Stamp (see Power Down Time-
Stamp, page 24) and the HT Bit (Halt Update) will
not be set during the power-down event. If both
are needed, the Power Down Time-Stamp may be
accomplished by writing the time into the General
Purpose RAM memory space when PFO is assert-
ed.
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相关代理商/技术参数 |
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| M41ST95WMH6E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
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