参数资料
型号: M41T81M6E
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO8
封装: 0.150 INCH, LEAD FREE, PLASTIC, SOIC-8
文件页数: 27/29页
文件大小: 454K
代理商: M41T81M6E
M41T81
Operation
Doc ID 7529 Rev 10
2
Operation
The M41T81 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1st byte: tenths/hundredths of a second register
2nd byte: seconds register
3rd byte: minutes register
4th byte: century/hours register
5th byte: day register
6th byte: date register
7th byte: month register
8th byte: year register
9th byte: control register
10th byte: watchdog register
11th - 16th bytes: alarm registers
17th - 19th bytes: reserved
20th byte: square wave register
The M41T81 clock continually monitors VCC for an out-of-tolerance condition. Should VCC
fall below VSO, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. The device also
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. As system power returns and VCC rises above VSO, the
battery is disconnected, and the power supply is switched to external VCC.
For more information on battery storage life refer to application note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
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