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参数资料
| 型号： | M470L6423CK0 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512MB DDR SDRAM MODULE (64Mx64 based on DDP 64Mx 8 DDR SDRAM) 200pin SODIMM 64bit Non-ECC/Parity |
| 中文描述： | 512MB的DDR SDRAM内存模组（64Mx64基于铂64Mx 8 DDR内存）200pin的SODIMM 64 Non-ECC/Parity |
| 文件页数： | 8/14页 |
| 文件大小： | 121K |
| 代理商： | M470L6423CK0 |
200pin DDR SDRAM SODIMM
M470L6423CK0
Rev. 0.0 Aug. 2001
I
DD7A
: Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
相关PDF资料 |
PDF描述 |
|---|---|
| M470L6423EN | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-A2 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-B0 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CB3 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CLB3 | 512MB Unbuffered SODIMM(based on sTSOP) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M470L6423EN | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-A2 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-B0 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CLB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
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