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参数资料
| 型号： | M48T212A-85MH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封装： | HATLESS, PLASTIC, SOIC-44 |
| 文件页数： | 15/30页 |
| 文件大小： | 155K |
| 代理商： | M48T212A-85MH6 |
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M48T212A
22/30
Figure 11. Back-up Mode Alarm Waveforms
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 7h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower-order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds). If the processor does not
reset the timer within the specified period, the
M48T212A sets the WDF (Watchdog Flag) and
generates a watchdog interrupt or a microproces-
sor reset. WDF is reset by reading the Flags Reg-
ister (Address 0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ’0.’ the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a ’1,’ the
watchdog will output a negative pulse on the RST
pin for 40 to 200 ms. The Watchdog Register,
AFE, ABE, and the FT Bits will reset to a ’0’ at the
end of a Watchdog time-out when the WDS Bit is
set to a ’1.’
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or
2. the microprocessor can perform a WRITE of the
Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec-
tively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register 0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the Frequency Test function is
activated, the watchdog or alarm function prevails
and the Frequency Test function is denied.
AI03622
VCC
IRQ/FT
HIGH-Z
VPFD (max)
VPFD (min)
AFE Bit/ABE Bit
AF Bit in Flags Register
HIGH-Z
tREC
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