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参数资料
| 型号： | M48T212A-85MH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封装： | HATLESS, PLASTIC, SOIC-44 |
| 文件页数： | 2/30页 |
| 文件大小： | 155K |
| 代理商： | M48T212A-85MH6 |
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M48T212A
10/30
OPERATION
Automatic backup and write protection for an ex-
ternal SRAM is provided through VOUT,E1CON
and E2CON pins. (Users are urged to insure that
voltage specifications, for both the SUPERVISOR
chip and external SRAM chosen, are similar).
The lithium energy source (or super capacitor)
used to permanently power the real time clock is
also used to retain RAM data in the absence of
VCC power through the VOUT pin.
The chip enable outputs to RAM (E1CON and
E2CON) are controlled during power transients to
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years (valid until 2100). The inter-
nal watchdog timer provides programmable alarm
windows.
The nine clock bytes (Fh-9h and 1h, see Table 13,
page 19) are not the actual clock counters, they
are memory locations consisting of BiPORTTM
READ/WRITE memory cells within the static RAM
array. Clock circuitry updates the clock bytes with
current information once per second. The informa-
tion can be accessed by the user in the same man-
ner as any other location in the static memory
array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
Bit (WDS). Bytes 6h-2h include bits that, when
programmed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
The M48T212A also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the TIMEKEEPER Register data
and external SRAM, providing data security in the
midst of unpredictable system operation. As VCC
falls, the control circuitry automatically switches to
the battery, maintaining data and clock operation
until valid power is restored.
Address Decoding
The M48T212A accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the SUPERVISOR chip it-
self. All TIMEKEEPER registers are accessed by
enabling E (Chip Enable).
Table 7. Operating Modes
Note: X = VIH or VIL;VSO = Battery Back-up Switchover Voltage
1. See Table 5, page 9 for details.
Mode
VCC
E
G
W
DQ7-DQ0
Power
Deselect
3.0V to 3.6V
VIH
X
High-Z
Standby
WRITE
VIL
X
VIL
DIN
Active
READ
VIL
VIH
DOUT
Active
READ
VIL
VIH
High-Z
Active
Deselect
VSO to VPFD (min)
(1)
X
High-Z
CMOS Standby
Deselect
≤ VSO(1)
X
High-Z
Battery Back-Up
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相关代理商/技术参数 |
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| M48T212A-85MH6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V TIMEKEEPER CONTROLLER |
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| M48T212V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V TIMEKEEPER supervisor |
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