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参数资料
| 型号： | M48T212A-85MH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封装： | HATLESS, PLASTIC, SOIC-44 |
| 文件页数： | 8/30页 |
| 文件大小： | 155K |
| 代理商： | M48T212A-85MH6 |
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M48T212A
16/30
Data Retention Mode
With valid VCC applied, the M48T212A can be ac-
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M48T212A will automatically deselect, write pro-
tecting itself (and any external SRAM) when VCC
falls between VPFD (max) and VPFD (min). This is
accomplished by internally inhibiting access to the
clock registers via the E signal. At this time, the
Reset pin (RST) is driven active and will remain
active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1CON and E2CON to a high level.
This level is within 0.2V of the VBAT.E1CON and
E2CON will remain at this level as long as VCC re-
mains at an out-of-tolerance condition.
When VCC falls below the level of the battery
(VBAT), power input is switched from the VCC pin
to the battery and the clock registers and external
SRAM are maintained from the attached battery
supply. All outputs become high impedance. The
VOUT pin is capable of supplying 100A of current
to the attached memory with less than 0.3V drop
under this condition. On power up, when VCC re-
turns to a nominal value, write protection contin-
ues for 200ms (max) by inhibiting E1CON or
E2CON.
The RST signal also remains active during this
time (see Figure 9, page 17).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212A TIMEKEEP-
ER SUPERVISOR. There are, however some
criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be de-
signed in a way where the chip enable input dis-
ables all other inputs to the SRAM. This allows
inputs to the M48T212A and SRAMs to be “Don’t
care” once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to VCC
= 2.0V. The chip enable access time must be suf-
ficient to meet the system needs with the chip en-
able output propagation delays included.
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M48T212A
to determine the total current requirements for
data retention. The available battery capacity can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T212A-85MH6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V TIMEKEEPER CONTROLLER |
| M48T212AMH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V TIMEKEEPER CONTROLLER |
| M48T212V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V TIMEKEEPER supervisor |
| M48T212V_07 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V TIMEKEEPER supervisor |
| M48T212V-70MH1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER[ CONTROLLER |
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