参数资料
型号: M48T35Y-70PC6
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP28
封装: 0.600 INCH, CAPHAT, PLASTIC, DIP-28
文件页数: 2/26页
文件大小: 349K
代理商: M48T35Y-70PC6
M48T35, M48T35Y
10/26
READ Mode
The M48T35/Y is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
Access time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV.
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (tAXQX) but will go indetermi-
nate until the next Address Access.
Figure 8. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. CL = 5pF.
Symbol
Parameter(1)
M48T35/Y
Unit
Min
Max
tAVAV
READ Cycle Time
70
ns
tAVQV
Address Valid to Output Valid
70
ns
tELQV
Chip Enable Low to Output Valid
70
ns
tGLQV
Output Enable Low to Output Valid
35
ns
tELQX
(2)
Chip Enable Low to Output Transition
5
ns
tGLQX
(2)
Output Enable Low to Output Transition
5
ns
tEHQZ
(2)
Chip Enable High to Output Hi-Z
25
ns
tGHQZ
(2)
Output Enable High to Output Hi-Z
25
ns
tAXQX
Address Transition to Output Transition
10
ns
AI00925
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A14
E
G
DQ0-DQ7
VALID
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