参数资料
型号: M48T35Y-70PC6
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP28
封装: 0.600 INCH, CAPHAT, PLASTIC, DIP-28
文件页数: 5/26页
文件大小: 349K
代理商: M48T35Y-70PC6
13/26
M48T35, M48T35Y
Data Retention Mode
With valid VCC applied, the M48T35/Y operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
when VCC falls within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T35/Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35/Y for
an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to exter-
nal VCC. Write protection continues until VCC
reaches VPFD (min) plus tREC (min). E should be
kept high as VCC rises past VPFD (min) to prevent
inadvertent WRITE Cycles prior to processor sta-
bilization. Normal RAM operation can resume tREC
after VCC exceeds VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
Figure 11. Power Down/Up Mode AC Waveforms
AI01168C
VCC
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tPD
tRB
tDR
VALID
(PER CONTROL INPUT)
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
tREC
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