参数资料
型号: M48T512Y-70PM1
厂商: 意法半导体
英文描述: Shielded Multiconductor Cable; Number of Conductors:5; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Conductor Material:Copper; Temperature Max:80 C RoHS Compliant: Yes
中文描述: 3.3 - 5V的4兆位的SRAM 512KB的x8计时器
文件页数: 8/14页
文件大小: 104K
代理商: M48T512Y-70PM1
M48T512Y, M48T512V
8/14
Table 10. Write Mode AC Characteristics
(T
A
= 0 to 70 °C)
Note: 1. C
L
= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48T512Y
M48T512V
Unit
-70
-85
Min
Max
Min
Max
t
AVAV
Write Cycle Time
70
85
ns
t
AVWL
Address Valid to Write Enable Low
0
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
0
ns
t
WLWH
Write Enable Pulse Width
50
60
ns
t
ELEH
Chip Enable Low to Chip Enable High
55
65
ns
t
WHAX
Write Enable High to Address Transition
5
5
ns
t
EHAX
Chip Enable High to Address Transition
10
15
ns
t
DVWH
Input Valid to Write Enable High
30
35
ns
t
DVEH
Input Valid to Chip Enable High
30
35
ns
t
WHDX
Write Enable High to Input Transition
5
5
ns
t
EHDX
Chip Enable High to Input Transition
10
15
ns
t
WLQZ
(1, 2)
Write Enable Low to Output Hi-Z
25
30
ns
t
AVWH
Address Valid to Write Enable High
60
70
ns
t
AVE1H
Address Valid to Chip Enable High
60
70
ns
t
WHQX
(1, 2)
Write Enable High to Output Transition
5
5
ns
Calibrating the Clock.
The M48T512Y/V is driv-
en by a quartz controlled oscillator with a nominal
frequency of 32,768Hz. The devices are factory
calibrated at 25°C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million)
oscillator frequency error at 25°C, which equates
to about ±1.53 minutes per month. When the Cal-
ibration circuit is properly employed, accuracy im-
proves to better than +4 ppm at 25°C. The
oscillation rate of crystals changes with tempera-
ture. The M48T512Y/V design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 10.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down. The Calibra-
tion bits occupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; '1' indicates positive
calibration, '0' indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 actual oscillator cycles; that
is, +4.068 or –2.034 ppm of adjustment per cali-
bration step in the calibration register.
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