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参数资料
| 型号： | M48T513Y-70PM1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP36 |
| 封装： | 0.600 INCH, PLASTIC, MODULE, DIP-36 |
| 文件页数： | 12/18页 |
| 文件大小： | 134K |
| 代理商： | M48T513Y-70PM1 |
3/18
M48T513Y, M48T513V
Figure 3. Block Diagram
AI02584
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
16 x 8
TIMEKEEPER
REGISTERS
524,272 x 8
SRAM ARRAY
A0-A18
DQ0-DQ7
E
W
G
POWER
RST
IRQ/FT
WDI
RSTIN
The M48T513Y/V includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
7FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering bit (WDS). Bytes 7FFF6h-7FFF2h in-
clude bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa-
tion. Byte 7FFF0h contains additional flag informa-
tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T513Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCC is out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un-
predictable system operation. As VCC falls, the
control circuitry automatically switches to the bat-
tery, maintaining data and clock operation until
valid power is restored.
READ MODE
The M48T513Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 524,272
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T513Y-85CS1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513Y-85PM1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513YPM | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513YSH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T559 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED |
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