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参数资料
| 型号： | M48T513Y-70PM1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP36 |
| 封装： | 0.600 INCH, PLASTIC, MODULE, DIP-36 |
| 文件页数： | 13/18页 |
| 文件大小： | 134K |
| 代理商： | M48T513Y-70PM1 |
M48T513Y, M48T513V
4/18
Table 3. Operating Modes (1)
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
VIH
X
High Z
Standby
Write
VIL
X
VIL
DIN
Active
Read
VIL
VIH
DOUT
Active
Read
VIL
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(2)
X
High Z
CMOS Standby
Deselect
≤ VSO (2)
X
High Z
Battery Back-up Mode
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
data and powering the clock. The internal energy
source will maintain data in the M48T513Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
tREC after VCC reaches VPFD (max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
WRITE MODE
The M48T513Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a write is referenced from the latter oc-
curring falling edge of W or E. A write is terminated
by the earlier rising edge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip
Enable or tWHAX from Write Enable prior to the ini-
tiation of another read or write cycle. Data-in must
be valid tDVWH prior to the end of write and remain
valid for tWHDX afterward. G should be kept high
during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a
low on E and G a low on W will disable the outputs
tWLQZ after W falls.
DATA RETENTION MODE
With valid VCC applied, the M48T513Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when VCC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as "don’t care".
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T513Y/V may re-
spond to transient noise spikes on VCC that cross
into the deselect window during the time the de-
vice is sampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
Figure 4. AC Testing Load Circuit
Note: Excluding open drain output pins.
AI01803C
CL = 100pF
CL includes JIG capacitance
650
DEVICE
UNDER
TEST
1.75V
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