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参数资料
| 型号： | M48T513Y-70PM1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP36 |
| 封装： | 0.600 INCH, PLASTIC, MODULE, DIP-36 |
| 文件页数： | 3/18页 |
| 文件大小： | 134K |
| 代理商： | M48T513Y-70PM1 |
11/18
M48T513Y, M48T513V
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
POWER-ON RESET
The M48T513Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for 40 to 200ms after VCC passes VPFD.
The RST pin is an open drain output and an appro-
priate pull-up resistor to VCC should be chosen to
control the rise time.
RESET INPUT (RSTIN)
The M48T513Y/V provides an independent input
which can generate an output reset. The duration
and function of this reset is identical to a reset gen-
erated by a power cycle. Table 13 and Figure 13
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than tR will not generate a re-
set condition. RSTIN is internally pulled up to VCC
through a 100K
resistor.
CALIBRATING THE CLOCK
The M48T513Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not ex-
ceed 35 ppm (parts per million) oscillator frequen-
cy error at 25°C, which equates to about * 1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than 4 ppm at 25°C. The oscillation rate of crystals
changes with temperature. The M48T513Y/V de-
sign employs periodic counter correction. The cal-
ibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage,
as shown in Figure 10.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down. The Calibra-
tion bits occupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; '1' indicates positive
calibration, '0' indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles.
Figure 9. Chip Enable Controlled, Write AC Waveforms
AI02582
tAVAV
tEHAX
tDVWH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEL
tAVWL
tELEH
tWHDX
DATA INPUT
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相关代理商/技术参数 |
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| M48T513Y-85CS1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513Y-85PM1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
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| M48T513YSH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
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