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参数资料
| 型号： | M50FLW080BN5G |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封装： | 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40 |
| 文件页数： | 14/64页 |
| 文件大小： | 534K |
| 代理商： | M50FLW080BN5G |
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M50FLW080A, M50FLW080B
Bus operations
Figure 7.
FWH Bus Write waveforms
Table 7.
FWH Bus Write field definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
START
1110b
I
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash Memory
is being addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address is transferred, with the most significant
nibble first. Address lines A20-21 and A23-27 are treated as
Don’t Care during a normal memory array access, with
A22=1, but are taken into account for a register access, with
A22=0. (See Table 15)
10
1
MSIZE
XXXX
I
0000(Single Byte Transfer) 0001 (Double Byte Transfer)
0010b (Quadruple Byte Transfer).
11-18
M=2/4/8
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble. (The first pair of nibbles is that at the address with A1-
A0 set to 00, the second pair with A1-A0 set to 01, the third
pair with A1-A0 set to 10, and the fourth pair with A1-A0 set
to 11. In Double Byte Program the first pair of nibbles is that
at the address with A0 set to 0, the second pair with A0 set to
1)
previous +1
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
previous +1
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3 during
this cycle.
previous +1
1
SYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
previous +1
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
previous +1
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
AI08434B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
DATA
TAR
SYNC
TAR
1171
M
212
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M50FLW080BN5P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
| M50FLW080BN5TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BNB5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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