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参数资料
型号： M50FLW080BN5G
厂商： STMICROELECTRONICS
元件分类： PROM
英文描述： 1M X 8 FLASH 3V PROM, 11 ns, PDSO40
封装： 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40
文件页数： 9/64页
文件大小： 534K
代理商： M50FLW080BN5G
M50FLW080A, M50FLW080B
Bus operations
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3
Bus operations
The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with different
bus signals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full
functionality, while the Address/Address Multiplexed (A/A Mux) Interface is orientated for
erase and program operations.
See the sections below, The Firmware Hub/low-pin-count (FWH/LPC) bus operations and
Address/Address multiplexed (A/A Mux) bus operations, for details of the bus operations on
each interface.
3.1
Firmware Hub/low-pin-count (FWH/LPC) bus operations
The M50FLW080 automatically identifies the type of FWH/LPC protocol from the first
received nibble (START nibble) and decodes the data that it receives afterwards, according
to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface
consists of four data signals (FWH0/LAD0-FWH3/LAD3), one control line (FWH4/LFRAME)
and a clock (CLK).
Protection against accidental or malicious data corruption is achieved using two additional
signals (TBL and WP). And two reset signals (RP and INIT) are available to put the memory
into a known state.
The data, control and clock signals are designed to be compatible with PCI electrical
specifications. The interface operates with clock speeds of up to 33MHz.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Standby, Reset and Block Protection.
3.1.1
Bus Read
Bus Read operations are used to read from the memory cells, specific registers in the
Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when the Input Communication Frame,
FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0-
FWH3/LAD3. On subsequent clock cycles the Host will send to the memory:
●
ID Select, Address and other control bits on FWH0-FWH3 in FWH mode.
●
Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode.
The device responds by outputting Sync data until the wait states have elapsed, followed by
Data0-Data3 and Data4-Data7.
See Table 6 and Table 8, and Figure 6 and Figure 8, for a description of the Field definitions
for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of
the signals.
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M50FLW080BN5P 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080BN5T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080BN5TG 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2
M50FLW080BN5TP 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080BNB5 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
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