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参数资料
| 型号： | M58LW128A150N1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 3V PROM, 150 ns, PDSO56 |
| 封装： | 14 X 20 MM, PLASTIC, TSOP-56 |
| 文件页数： | 4/65页 |
| 文件大小： | 378K |
| 代理商： | M58LW128A150N1 |
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M58LW128A, M58LW128B
12/65
the outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The
Reset/Power-
Down pin can be used to apply a Hardware Reset
to the memory or to temporarily unprotect all
blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, VIL, for at least tPLPH. When
Reset/Power-Down is Low, VIL, the Status Regis-
ter information is cleared and the current is re-
duced
to
IDD2
(refer
to
Table
16,
DC
Characteristics). The device is deselected and
outputs are high impedance. If Reset/Power-
Down goes low, VIL,during a Block Erase, a Write
to Buffer and Program or a Block Protect/Unpro-
tect the operation is aborted and the data may be
corrupted. In this case the Ready/Busy pin stays
low, VIL, for a maximum timing of tPLPH +tPHRH.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read and Bus Write
operations after tRHEL. Note that Ready/Busy does
not fall during a reset, see Ready/Busy Output
section.
During power-up Reset/Power-Down must be held
Low, VIL. Furthermore it must stay low for tVDHPH
after the Supply Voltage inputs become stable.
The device will then be configured in Asynchro-
nous Random Read mode.
See Table 23 and Figure 21, Reset, Power-Down
and Power-up Characteristics, for more details.
Holding RP at VHH will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing a pro-
gram or erase operation, the memory may output
the Status Register information instead of being
initialized to the default Asynchronous Random
Read.
Latch Enable (L). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L. In synchronous bus oper-
ations the address is latched on the active edge of
the Clock when Latch Enable is Low, VIL. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
Enable is Low, VIL, the latch is transparent.
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
low, VIL, or on the rising edge of Latch Enable,
whichever occurs first.
During Asynchronous Bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during synchro-
nous bus operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X- or Y-
latency time has expired. If Burst Address Ad-
vance is Low, VIL, the internal address counter ad-
vances. If Burst Address Advance is High, VIH, the
internal address counter does not change; the
same data remains on the Data Inputs/Outputs
and Burst Address Advance is not sampled until
the Y-latency expires.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
one cycle before. Valid Data Ready Low, VOL, in-
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
Unless the Burst Length is set to Continuous and
Synchronous Burst Read has been selected, Valid
Data Ready is high-impedance. It may be tied to
other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
When the system clock frequency is between
33MHz and 50MHz and the Y latency is set to 2,
values of B sampled on odd clock cycles, starting
from the first read are not considered.
Designers should use an external pull-up resistor
of the correct value to meet the external timing re-
quirements for Valid Data Ready rising. Refer to
Figure 20.
Word Organization (WORD). The Word Organi-
zation input, WORD, selects the x16 or x32 Bus
Width on the M58LW128B. The Word Organiza-
tion input is not available on the M58LW128A.
When WORD is Low, VIL, Word-wide x16 Bus
Width is selected; data is read and written to DQ0-
DQ15; DQ16-DQ31 are at high impedance and A1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M58LW128A150N1E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128A150N1F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128A150N1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128A150N6E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128A150N6F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
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