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参数资料
型号： M58LW128A150N1
厂商： STMICROELECTRONICS
元件分类： PROM
英文描述： 8M X 16 FLASH 3V PROM, 150 ns, PDSO56
封装： 14 X 20 MM, PLASTIC, TSOP-56
文件页数： 6/65页
文件大小： 378K
代理商： M58LW128A150N1
M58LW128A, M58LW128B
14/65
BUS OPERATIONS
The bus operations that control the memory are
described in this section, see Tables 2 and 3, Bus
Operations, for a summary. The bus operation is
selected through the Burst Configuration Register;
the bits in this register are described at the end of
this section.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write, no other bus operation can
be performed until the Burst Control Register has
been configured.
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in asynchro-
nous mode regardless of the Burst Control Regis-
ter settings.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus Operations
For asynchronous bus operations refer to Table 3
together with the text below.
Asynchronous Bus Read. Asynchronous
Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Block Protection Status) in the
Command Interface. A valid bus operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 12, Asynchronous Bus Read AC
Waveforms, and Table 17, Asynchronous Bus
Read AC Characteristics, for details of when the
output becomes valid.
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Address Latch Low, VIL and keeping
Write Enable High, VIH; the address is latched on
the rising edge of Address Latch. Once latched,
the Address Inputs can change. Set Output En-
able Low, VIL, to read the data on the Data Inputs/
Outputs; see Figure 13, Asynchronous Latch Con-
trolled Bus Read AC Waveforms and Table 18,
Asynchronous Latch Controlled Bus Read AC
Characteristics for details on when the output be-
comes valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
Asynchronous Page Read. Asynchronous Page
Read operations are used to read from several ad-
dresses within the same memory page. Each
memory page is 8 Words or 4 Double-Words and
has the same A4-A23, only A1, A2 and A3 may
change.
Valid bus operations are the same as Asynchro-
nous Bus Read operations but with different tim-
ings. The first read operation within the page has
identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. See Figure 14, Asynchronous Page
Read AC Waveforms and Table 19, Asynchro-
nous Page Read AC Characteristics for details on
when the outputs become valid.
Asynchronous Bus Write. Asynchronous
Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts and setting Latch Enable Low, VIL. The Ad-
dress Inputs are latched by the Command
Interface on the rising edge of Chip Enable or
Write Enable, whichever occurs first. The Data In-
puts/Outputs are latched by the Command Inter-
face on the rising edge of Chip Enable or Write
Enable, whichever occurs first. Output Enable
must remain High, VIH, during the whole Asyn-
chronous Bus Write operation. See Figures 15,
and 17, Asynchronous Write AC Waveforms, and
Tables 20 and 21, Asynchronous Write and Latch
Controlled Write AC Characteristics, for details of
the timing requirements.
Asynchronous Latch Controlled Bus Write.
Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
VIL. The Address Inputs are latched by the Com-
mand Interface on the rising edge of Latch Enable,
Chip Enable or Write Enable, whichever occurs
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相关代理商/技术参数
参数描述
M58LW128A150N1E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128A150N1F 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128A150N1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128A150N6E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128A150N6F 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
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