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参数资料
| 型号： | M5LV-128/74-15VI |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 34/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MC 74I/O 100TQFP |
| 标准包装： | 90 |
| 系列： | MACH® 5 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 宏单元数： | 128 |
| 输入/输出数： | 74 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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4
MACH 5 Family
and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test
Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block
interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the
segments together. The only logic difference between any two MACH 5 devices is the number of segments.
Therefore, once a designer is familiar with one device, consistent performance can be expected across the
entire family. All devices have four clock pins available which can also be used as logic inputs.
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an
independent PAL device, it has superior control and logic generation capabilities.
◆ I/O cells
◆ Product-term array and Logic Allocator
◆ Macrocells
◆ Register control generator
◆ Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local feedback.
If the I/O is used in another PAL block, the
interconnect feeder assigns a block interconnect line to that
signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide
connections between any two signals in a device. The
block feeder assigns block interconnect lines and local
feedback lines to the PAL block inputs.
Block
Interconnect
4
CLK
Block:
16 MCs
Segment:
4 Blocks
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| M5LV-128/74-12VC | IC CPLD 128MC 74I/O 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M5LV-256/104-10AC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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